?? nand.c
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#elif TRANS_MODE==DMA
// Memory to Nand dma setting
rSUBSRCPND=BIT_SUB_DMA0;
rSRCPND=BIT_DMA; // Init DMA src pending.
rDISRC0=(unsigned)bufPt; // Nand flash data register
rDISRCC0=(0<<1) | (0<<0); //arc=AHB,src_addr=inc
rDIDST0=NFDATA;
rDIDSTC0=(0<<1) | (1<<0); //dst=AHB,dst_addr=fix;
rDCON0=(1<<31)|(1<<30)|(1<<29)|(0<<28)|(1<<27)|(0<<23)|(1<<22)|(2<<20)|(2048/4);
// only unit transfer in writing!!!!
//Handshake,AHB,interrupt,(unit),whole,S/W,no_autoreload,word,count=128;
// DMA on and start.
rDMASKTRIG0=(1<<1)|(1<<0);
while(!(rSUBSRCPND & BIT_SUB_DMA0)); // Wait until Dma transfer is done.
rSUBSRCPND=BIT_SUB_DMA0;
rSRCPND=BIT_DMA;
#endif
/*
NF_MECC_Lock();
// Get ECC data.
// Spare data for 8bit
// byte 0 1 2 3 4 5
// ecc [0] [1] [2] [3] x [Bad marking]
Mecc = rNFMECC0;
se8Buf[0]=(U8)(Mecc&0xff);
se8Buf[1]=(U8)((Mecc>>8) & 0xff);
se8Buf[2]=(U8)((Mecc>>16) & 0xff);
se8Buf[3]=(U8)((Mecc>>24) & 0xff);
se8Buf[5]=0xffff; // Marking good block
//Write extra data(ECC, bad marking)
for(i=0;i<16;i++) {
NF_WRDATA8(se8Buf[i]); // Write spare array(ECC and Mark)
NF8_Spare_Data[i]=se8Buf[i];
}
NF_CLEAR_RB();
NF_CMD(0x10); // Write 2nd command
NF_DETECT_RB();
NF_CMD(0x70); // Read status command
for(i=0;i<3;i++); //twhr=60ns
if (NF_RDDATA()&0x1) {// Page write error
Uart_Printf("[PROGRAM_ERROR:block#=%d]\n",block);
NF8_MarkBadBlock(block);
NF_nFCE_H();
return FAIL;
} else {
NF_nFCE_H();
return OK;
}
*/
NF_MECC_Lock();
// Get ECC data.
// Spare data for 8bit
// byte 0 1 2 3 4 5 6 7 8 9
// ecc [Bad marking] [0] [1] [2] [3] x SECC0 SECC1
Mecc = rNFMECC0;
Adv_se8Buf[0]=0xff;
Adv_se8Buf[1]=(U8)(Mecc&0xff);
Adv_se8Buf[2]=(U8)((Mecc>>8) & 0xff);
Adv_se8Buf[3]=(U8)((Mecc>>16) & 0xff);
Adv_se8Buf[4]=(U8)((Mecc>>24) & 0xff);
// Marking good block
NF_SECC_UnLock();
//Write extra data(ECC, bad marking)
for(i=0;i<8;i++) {
NF_WRDATA8(Adv_se8Buf[i]); // Write spare array(Main ECC)
Adv_NF8_Spare_Data[i]=Adv_se8Buf[i];
}
NF_SECC_Lock();
Secc=rNFSECC;
Adv_se8Buf[8]=(U8)(Secc&0xff);
Adv_se8Buf[9]=(U8)((Secc>>8) & 0xff);
for(i=5;i<64;i++) {
NF_WRDATA8(Adv_se8Buf[i]); // Write spare array(Spare ECC and Mark)
Adv_NF8_Spare_Data[i]=Adv_se8Buf[i];
}
NF_CLEAR_RB();
NF_CMD(0x10); // Write 2nd command
// NF_DETECT_RB();
while(NFConDone==0);
rNFCONT&=~(1<<9);
rNFCONT&=~(1<<10); // Disable Illegal Access Interrupt
if(rNFSTAT&0x20) return FAIL;
NF_CMD(0x70); // Read status command
for(i=0;i<3;i++); //twhr=60ns
if (NF_RDDATA()&0x1) {// Page write error
NF_nFCE_H();
printf("[PROGRAM_ERROR:block#=%d]\n",block);
NF8_MarkBadBlock(block);
return FAIL;
} else {
NF_nFCE_H();
return OK;
}
}
static U16 NF8_CheckId(void)
{
int i;
U16 id, id4th;
// rEBICON|=(1<<8);
NF_nFCE_L();
// NF_nCS1_L();
NF_CMD(0x90);
NF_ADDR(0x0);
for (i=0; i<10; i++);
// printf("NFSTAT: 0x%x\n", rNFSTAT);
id=NF_RDDATA8()<<8; // Maker code 0xec
id|=NF_RDDATA8(); // Devide code(K9S1208V:0x76), (K9K2G16U0M:0xca)
NF_nFCE_H();
// NF_nCS1_H();
return id;
}
void Nand_Reset(void)
{
int i;
NF_nFCE_L();
NF_CLEAR_RB();
NF_CMD(0xFF); //reset command
for(i=0;i<10;i++); //tWB = 100ns. //??????
NF_DETECT_RB();
NF_nFCE_H();
}
static void NF8_Init(void)
{
// for S3C2413
rNFCONF = (TACLS<<12)|(TWRPH0<<8)|(TWRPH1<<4)|(0<<0);
// TACLS [14:12] CLE&ALE duration = HCLK*TACLS.
// TWRPH0 [10:8] TWRPH0 duration = HCLK*(TWRPH0+1)
// TWRPH1 [6:4] TWRPH1 duration = HCLK*(TWRPH1+1)
// AdvFlash(R) [3] Advanced NAND, 0:256/512, 1:1024/2048
// PageSize(R) [2] NAND memory page size
// when [3]==0, 0:256, 1:512 bytes/page.
// when [3]==1, 0:1024, 1:2048 bytes/page.
// AddrCycle(R) [1] NAND flash addr size
// when [3]==0, 0:3-addr, 1:4-addr.
// when [3]==1, 0:4-addr, 1:5-addr.
// BusWidth(R/W) [0] NAND bus width. 0:8-bit, 1:16-bit.
//rNFCONT = (0<<17)|(0<<16)|(0<<10)|(0<<9)|(0<<8)|(1<<7)|(1<<6)|(1<<5)|(1<<4)|(1<<1)|(1<<0);
rNFCONT = (0<<17)|(0<<16)|(0<<10)|(0<<9)|(0<<8)|(1<<7)|(1<<6)|(1<<5)|(1<<4)|(0x3<<1)|(1<<0);
// Lock-tight [17] 0:Disable lock, 1:Enable lock.
// Soft Lock [16] 0:Disable lock, 1:Enable lock.
// EnablillegalAcINT[10] Illegal access interupt control. 0:Disable, 1:Enable
// EnbRnBINT [9] RnB interrupt. 0:Disable, 1:Enable
// RnB_TrandMode[8] RnB transition detection config. 0:Low to High, 1:High to Low
// SpareECCLock [7] 0:Unlock, 1:Lock
// MainECCLock [6] 0:Unlock, 1:Lock
// InitMECC(W) [5] 1:Init main area ECC decoder/encoder.
// InitSECC(W) [4] 1:Init spare area ECC decoder/encoder.
// Reg_nCE1 [2] 0:nFCE=0, 1:nFCE=1.
// Reg_nCE0 [1] 0:nFCE=0, 1:nFCE=1.
// NANDC Enable [0] operating mode. 0:Disable, 1:Enable.
// rNFSTAT = 0;
// Nand_Reset();
}
#define SRAM_SADDR 0x40000000
#define SRAM_EADDR (SRAM_SADDR+ (4*1024)) // Total : 4KB, 0x3100_0000-0x3101_FFFF
void SRAM_Test(int Print_msg)
{
U32 addr=0, indata, src_data, i;
U32 error;
static int offset=0;
U16 jump_offset=1;
//printf("Check: SRAM Area must be in non-cacheable area!\n");
//printf("SRAM W/R test[%xh-%xh], R/W offset[%d]\n", SRAM_SADDR, SRAM_EADDR-1, offset);
for(i=0; i<3; i++) { // 8/16/32-bit.
// for(i=2; i<3; i++) { // 8/16/32-bit.
if(i==0) jump_offset=1;
else if(i==1) jump_offset=2;
else if(i==2) jump_offset=4;
///////////////////// Clear Source/Target ////////////////////
//printf("Clear data.\n");
for(addr=0; (SRAM_SADDR+addr)<SRAM_EADDR; addr+=4) {
*(U32 *)(SRAM_SADDR+addr) = 0x0;
if(!(addr%(4*1024))) {
//printf("\b\b\b\b\b\b\b\b\b\b%10x", SRAM_SADDR+addr);
}
}
//printf("\b\b\b\b\b\b\b\b\b\b%10x\n", SRAM_SADDR+addr);
///////////////////// Write ////////////////////
//printf("Write data[%x-%x].\n", SRAM_SADDR, SRAM_EADDR);
if(Print_msg>0) printf("Wr(%d-bit)...", jump_offset*8);
if(Print_msg>1) printf("ADDR:%8x", SRAM_SADDR);
Led_Display(0x1);
for(addr=0; (SRAM_SADDR+addr)<SRAM_EADDR; addr+=jump_offset) {
src_data = addr+offset;
switch(jump_offset) {
case 1:
*(U8 *)(SRAM_SADDR+addr) = src_data;
break;
case 2:
*(U16 *)(SRAM_SADDR+addr) = src_data;
break;
case 4:
*(U32 *)(SRAM_SADDR+addr) = src_data;
break;
}
if(!(addr%(4*1024))) {
if(Print_msg>1) printf("\b\b\b\b\b\b\b\b%8x", SRAM_SADDR+addr);
}
}
if(Print_msg>1) printf("\b\b\b\b\b\b\b\b%8x ", SRAM_SADDR+addr);
///////////////////// Verify //////////////////////
//printf("Verify[%x-%x].\n", SRAM_SADDR, SRAM_EADDRs
if(Print_msg>1) printf("ADDR:%8x", SRAM_SADDR);
Led_Display(0x2);
for(error=0, addr=0; (SRAM_SADDR+addr)<SRAM_EADDR; addr+=jump_offset) {
switch(jump_offset) {
case 1:
src_data = (U8)(addr+offset);
indata = *(U8 *)(SRAM_SADDR+addr);
break;
case 2:
src_data = (U16)(addr+offset);
indata = *(U16 *)(SRAM_SADDR+addr);
break;
case 4:
src_data = (U32)(addr+offset);
indata = *(U32 *)(SRAM_SADDR+addr);
break;
}
if(!(addr%(4*1024))) {
if(Print_msg>1) printf("\b\b\b\b\b\b\b\b%8x", SRAM_SADDR+addr);
}
indata = indata|0x800;
if(indata != (src_data|0x800)) {
error++;
printf("%xH[W:%x, R:%x]\n", addr, src_data, indata);
}
}
if(Print_msg>1) printf("\b\b\b\b\b\b\b\b%8x ", SRAM_SADDR+addr);
if(error!=0) {
if(Print_msg>0) printf("ERROR(%d)...\n\n", error);
} else {
if(Print_msg>0) printf("OK!\n");
//printf(".");
}
Led_Display(0xf);
}
offset++;
}
void Test_MLC_Adv_ECC(void)
{
int i;
U32 block, page;
U32 blockPage, Mecc0, Mecc1, Mecc2, Mecc3, Mecc4, Mecc5, Mecc6, Mecc7, Secc;
//U8 *bufPt=buffer;
U8 *bufPt;
Adv_NF8_EraseBlock(1);
bufPt=(unsigned char *)0x31100000;
NFConDone=0, NFECCEncDone=0, NFECCDecDone=0;
rNFCONF = (rNFCONF & ~(1<<30))|(1<<24); // System Clock is more than 66Mhz, ECC type is MLC.
rNFCONT |= (1<<18); //ECC for programming.
rNFCONT|=(1<<9); // Enable RnB Interrupt
rNFCONT|=(1<<10); // Enable Illegal Access Interrupt
rNFCONT|=(1<<13); // Enable ECC encoding & decoding conpletion interrupt enable
rNFCONT|=(1<<12); // Enable ECC encoding & decoding conpletion interrupt enable
pISR_NFCON= (unsigned)NFCon_Int;
rSRCPND=BIT_NFCON;
rINTMSK&=~(BIT_NFCON);
/////////////////////////////////////////////////
// block1, page0 writing with valid data, ecc /
/////////////////////////////////////////////////
block=1;
page=0;
blockPage=(block<<6)+page;
NF_nFCE_L();
NF_CMD(0x0);//??????
NF_CMD(0x80); // Write 1st command
NF_ADDR(0); // Column (A[7:0]) = 0
NF_ADDR(0); // A[11:8]
NF_ADDR((blockPage)&0xff); // A[19:12]
NF_ADDR((blockPage>>8)&0xff); // A[27:20]
NF_ADDR((blockPage>>16)&0xff); // A[27:20]
// 0~511
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
rNFCONT=0x43075;
for(i=0;i<512;i++) {
NF_WRDATA8(i); // Write one page to NFM from buffer
}
while(!(rNFSTAT&(1<<7))) ;
rNFSTAT|=(1<<7);
Mecc0 = rNFMECC0;
Mecc1 = rNFMECC1;
// 512~1023
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
for(i=512;i<1024;i++) {
NF_WRDATA8(i); // Write one page to NFM from buffer
}
while(!(rNFSTAT&(1<<7))) ;
rNFSTAT|=(1<<7);
Mecc2 = rNFMECC0;
Mecc3 = rNFMECC1;
// 1024~1535
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
for(i=1024;i<1536;i++) {
NF_WRDATA8(i); // Write one page to NFM from buffer
}
while(!(rNFSTAT&(1<<7))) ;
rNFSTAT|=(1<<7);
Mecc4 = rNFMECC0;
Mecc5 = rNFMECC1;
// 1536~2047
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
for(i=1536;i<2048;i++) {
NF_WRDATA8(i); // Write one page to NFM from buffer
}
while(!(rNFSTAT&(1<<7))) ;
rNFSTAT|=(1<<7);
Mecc6 = rNFMECC0;
Mecc7 = rNFMECC1;
// Get ECC data.
// Spare data for 8bit
// byte 0 1 2 3 4 5 6 7 8 9
// ecc [0] [1] [2] [3] [4] [5] [6]
Adv_se8Buf[1]=(U8)(Mecc0&0xff);
Adv_se8Buf[2]=(U8)((Mecc0>>8) & 0xff);
Adv_se8Buf[3]=(U8)((Mecc0>>16) & 0xff);
Adv_se8Buf[4]=(U8)((Mecc0>>24) & 0xff);
Adv_se8Buf[5]=(U8)(Mecc1&0xff);
Adv_se8Buf[6]=(U8)((Mecc1>>8) & 0xff);
Adv_se8Buf[7]=(U8)((Mecc1>>16) & 0xff);
Adv_se8Buf[8]=(U8)(Mecc2&0xff);
Adv_se8Buf[9]=(U8)((Mecc2>>8) & 0xff);
Adv_se8Buf[10]=(U8)((Mecc2>>16) & 0xff);
Adv_se8Buf[11]=(U8)((Mecc2>>24) & 0xff);
Adv_se8Buf[12]=(U8)(Mecc3&0xff);
Adv_se8Buf[13]=(U8)((Mecc3>>8) & 0xff);
Adv_se8Buf[14]=(U8)((Mecc3>>16) & 0xff);
Adv_se8Buf[15]=(U8)(Mecc4&0xff);
Adv_se8Buf[16]=(U8)((Mecc4>>8) & 0xff);
Adv_se8Buf[17]=(U8)((Mecc4>>16) & 0xff);
Adv_se8Buf[18]=(U8)((Mecc4>>24) & 0xff);
Adv_se8Buf[19]=(U8)(Mecc5&0xff);
Adv_se8Buf[20]=(U8)((Mecc5>>8) & 0xff);
Adv_se8Buf[21]=(U8)((Mecc5>>16) & 0xff);
Adv_se8Buf[22]=(U8)(Mecc6&0xff);
Adv_se8Buf[23]=(U8)((Mecc6>>8) & 0xff);
Adv_se8Buf[24]=(U8)((Mecc6>>16) & 0xff);
Adv_se8Buf[25]=(U8)((Mecc6>>24) & 0xff);
Adv_se8Buf[26]=(U8)(Mecc7&0xff);
Adv_se8Buf[27]=(U8)((Mecc7>>8) & 0xff);
Adv_se8Buf[28]=(U8)((Mecc7>>16) & 0xff);
for(i=0;i<64;i++) {
NF_WRDATA8(Adv_se8Buf[i]); // Write spare array(Main ECC)
Adv_NF8_Spare_Data[i]=Adv_se8Buf[i];
}
NF_CLEAR_RB();
NF_CMD(0x10); // Write 2nd command
NF_DETECT_RB();
// while(NFConDone==0);
rNFCONT&=~(1<<9);
rNFCONT&=~(1<<10); // Disable Illegal Access Interrupt
if(rNFSTAT&0x20)
{
printf("Illegal access Error\n");
return;
}
NF_CMD(0x70); // Read status command
for(i=0;i<3;i++); //twhr=60ns
if (NF_RDDATA8()&0x1) {// Page write error
NF_nFCE_H();
printf("first[PROGRAM_ERROR:block#=%d]\n",block);
// Adv_NF8_MarkBadBlock(block);
return;
} else {
NF_nFCE_H();
}
/////////////////////////////////////////////////
// block1, page1 writing with invalid data, ecc /
/////////////////////////////////////////////////
NFConDone=0;
rSRCPND=BIT_NFCON;
rINTMSK=~(BIT_NFCON);
NF_RSTECC(); // Initialize ECC
NF_MECC_UnLock();
block=1;
page=1;
blockPage=(block<<6)+page;
NF_nFCE_L();
NF_CMD(0x0);//??????
NF_CMD(0x80); // Write 1st command
NF_ADDR(0); // Column 0
NF_ADDR(0); // Column 0
NF_ADDR(blockPage&0xff); //
NF_ADDR((blockPage>>8)&0xff); // Block & page num.
NF_ADDR((blockPage>>16)&0xff); //
//NF_RSTECC(); // Initialize ECC
#if 0 //1-bit Error
for(i=0;i<512;i++) {
NF_WRDATA8(i);
}
#elif 0 //1-bit Error
for(i=0;i<512;i++) {
if(i==200) {
NF_WRDATA8(0xc0);
}
else {
NF_WRDATA8(i);
}
}
#elif 0 //2-bit Error
for(i=0;i<512;i++) {
if(i==128) {
NF_WRDATA8(129);
}
else if(i==255) {
NF_WRDATA8(0x7f);
}
else {
NF_WRDATA8(i);
}
}
#elif 0 //3-bit Error
for(i=0;i<512;i++) {
if(i==10) {
NF_WRDATA8(11);
}
else if(i==511) {
NF_WRDATA8(0xdf);
}
else if(i==128) {
NF_WRDATA8(0x82);
}
else {
NF_WRDATA8(i);
}
}
#elif 1 // 4-bit Error
for(i=0;i<512;i++) {
if(i==10) {
NF_WRDATA8(11);
}
else if(i==500) {
NF_WRDATA8(0xf0);
}
else if(i==200) {
NF_WRDATA8(0xc0);
}
else if(i==30) {
NF_WRDATA8(0x16);
}
else {
NF_WRDATA8(i);
}
}
#endif
while(!(rNFSTAT&(1<<7))) ;
//while(NFECCEncDone==0);
rNFSTAT|=(1<<7);
Mecc0 = rNFMECC0;
Mecc1 = rNFMECC1;
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