--    File Name:  me.vhd--    Version:  1.0--    Date:  January 22, 2000--    Model:  Manchester Encoder Chip----    Company:  Xilinx------   Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY --                WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY --                IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR--                A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.----                Copyright (c) 2000 Xilinx, Inc.--                All rights reservedlibrary ieee ;use ieee.std_logic_1164.all ;use ieee.std_logic_arith.all ;use ieee.std_logic_unsigned.all ;entity me isport (rst,clk16x,wrn : in std_logic ;	din : in std_logic_vector (7 downto 0) ;	tbre : out std_logic ;	mdo   : out std_logic ) ;end me ;architecture v1 of me issignal clk1x : std_logic ;signal clk1x_enable : std_logic ;signal clkdiv : std_logic_vector (3 downto 0) ;signal tsr : std_logic_vector (7 downto 0) ;signal tbr : std_logic_vector (7 downto 0) ;signal parity : std_logic ;signal no_bits_sent : std_logic_vector (3 downto 0) ;signal wrn1 : std_logic ;signal wrn2 : std_logic ;signal clk1x_disable : std_logic ;begin-- Form two bit register for write pulseprocess (rst,clk16x,wrn,wrn1,wrn2)beginif rst = '1' thenwrn2 <= '1' ;wrn1 <= '1' ;elsif clk16x'event and clk16x = '1' thenwrn2 <= wrn1 ;wrn1 <= wrn ;end if ;end process ;-- Enable clock when detect edge on write pulse process (rst,clk16x,wrn1,wrn2,no_bits_sent)beginif rst = '1' or std_logic_vector(no_bits_sent) = "1010" thenclk1x_enable <=  '0' ;elsif clk16x'event and clk16x = '1' thenif (wrn1 = '1' and wrn2 = '0')  then clk1x_enable <= '1' ;elsif std_logic_vector(no_bits_sent) = "1001" thenclk1x_enable <= '0' ;end if ;end if ;end process ;-- Generate Transmit Buffer Register Empty signalprocess (rst,clk16x,wrn1,wrn2,no_bits_sent)beginif rst = '1' thentbre <= '1' ;elsif clk16x'event and clk16x = '1' thenif (wrn1 = '1' and wrn2 = '0')  thentbre <= '0' ;elsif (std_logic_vector(no_bits_sent) = "0010") thentbre <= '1' ;else tbre <= '0' ;end if ;end if ;end process ;-- Detect edge on write pulse to load transmit bufferprocess (rst,clk16x,wrn1,wrn2)beginif rst = '1' then tbr <= "00000000" ;elsif clk16x'event and clk16x = '0' thenif wrn1 = '1' and wrn2 = '0' thentbr <= din ;end if ;end if ;end process ;-- Increment clock process (rst,clk16x,clkdiv,clk1x_enable)beginif rst = '1' thenclkdiv <= "0000" ;elsif clk16x'event and clk16x = '1' thenif clk1x_enable = '1' thenclkdiv <= clkdiv + "0001" ;end if ;end if ;end process ;clk1x <= clkdiv(3) ;-- Load TSR from TBR, shift TSRprocess (rst,clk1x,no_bits_sent,tsr)beginif rst = '1' thentsr <= "00000000" ;elsif clk1x'event and clk1x = '1' thenif std_logic_vector(no_bits_sent) = "0001" thentsr <= tbr ;elsif std_logic_vector(no_bits_sent) >= "0010" and std_logic_vector(no_bits_sent) <= "1010" thentsr <= tsr(6 downto 0)  & '0' ;elsetsr <= tsr ;end if ;end if ;end process ;-- Generate Manchester data from NRZmdo <= tsr(7) xor clk1x ;-- Generate parityprocess (rst,clk1x,tsr(7))beginif rst = '1' then parity <= '0' ;elsif clk1x'event and clk1x = '1' thenparity <= parity xor tsr(7) ;end if ;end process ;-- Calculate the number of bits sentprocess (clk1x,rst,clk1x_disable,clk1x_enable,no_bits_sent)begin if rst = '1' or clk1x_disable = '1' thenno_bits_sent <= "0000" ;elsif clk1x'event and clk1x = '1'  thenif clk1x_enable = '1' thenno_bits_sent <= no_bits_sent + "0001" ;end if  ;end if  ;end process ;clk1x_disable <= not clk1x_enable ;end ;