* type value defined in this file.** INTERNAL* The PCI Vendor and Device IDs are the same for all driver supported* Am79c97x devices.  When an instance is located, the PCI Revision ID is* used to determine whether or not the driver can support the device.** The shift and mask operations used to implement this routine are based* upon the following table which documents the PCI Revison ID register* values one can expect for the devices we are supporting:** ---------------------------------------------------------------------------*      PCI Configuration Space Offset: 0x08 PCI Revision ID Register** 31               16  15                0* xxxx xxxx xxxx xxxx  xxxx xxxx RRRR RRRR* xxxx xxxx xxxx xxxx  xxxx xxxx 0000 xxxx 0x  Am79C970  PCnet-PCI* xxxx xxxx xxxx xxxx  xxxx xxxx 0001 xxxx 1x  Am79C970A PCnet-PCI II* xxxx xxxx xxxx xxxx  xxxx xxxx 0010 xxxx 2x  Am79C971  PCnet-FAST* xxxx xxxx xxxx xxxx  xxxx xxxx 0011 xxxx 3x  Am79C972  PCnet-FAST+* xxxx xxxx xxxx xxxx  xxxx xxxx 0100 xxxx 4x  Am79C973  PCnet-FAST III* xxxx xxxx xxxx xxxx  xxxx xxxx 0100 xxxx 4x  Am79C975  PCnet-FAST III* xxxx xxxx xxxx xxxx  xxxx xxxx 0101 xxxx 5x  Am79C978  PCnet-Home* ---------------------------------------------------------------------------** While the driver documentation is not specific on the matter, the* revision ID is required because the driver supports Am79C970A* (PCnet-PCI II), but not Am79C970 (PCnet-PCI).  Moreover, AMD's* documentation indicates that Am79C973 devices and Am79C975 devices* will be identified as the same revision.** RETURNS:* A board type value which will be one of** .IP* LN_TYPE_970* .IP* LN_TYPE_971* .IP* LN_TYPE_972* .IP* LN_TYPE_973* .LP** BOARD_TYPE_UNKNOWN will be returned if the Revision ID does not map to* a supported board type.** NOMANUAL*/LOCAL UINT32 sysLn97xDev2Type    (    UINT32 vendorId,    /* specifies a PCI vendor ID value */    UINT32 deviceId,    /* specifies a PCI device ID value */    UINT8  revisionId   /* specifies a PCI revision ID value */    )    {    if ((vendorId == AMD_PCI_VENDOR_ID) &&        (deviceId == LN97X_PCI_DEVICE_ID))        {        /* An AMD Am79C97x board was found.  Check the         * Revision ID and make sure we support it.         */        if ((revisionId & LN970_PCI_REV_MASK) ||            (revisionId & LN971_PCI_REV_MASK) ||            (revisionId & LN972_PCI_REV_MASK) ||            (revisionId & LN973_PCI_REV_MASK))            {            /* assume the shifted Revision ID is one of LN_TYPE_97x */            return (UINT32)(revisionId >> 4);            }        }    return (BOARD_TYPE_UNKNOWN);    }/********************************************************************************* sysLan97xPciInit - initialize a Am79C97x PCI ethernet device*** This routine performs basic PCI initialization for Am79C97x ethernet* devices supported by the ln97xEnd END driver.  If supported,  the device* memory and I/O addresses are mapped into the local CPU address space and* an internal board-specific PCI resources table is updated with* information on the board type, memory address, and IO address.** CAVEATS* This routine must be performed prior to MMU initialization, usrMmuInit().* If the number of supported Am79c97x physical device instances installed* on the PCI bus exceeds LN97X_MAX_DEV, then the extra devices will not be* initialized in this routine.** RETURNS:* OK, else ERROR when the specified device is not supported, or if* the device could not be mapped into the local CPU memory space.*/STATUS sysLan97xPciInit    (    UINT32  pciBus,           /* store a PCI bus number */    UINT32  pciDevice,        /* store a PCI device number */    UINT32  pciFunc,          /* store a PCI function number */    UINT32  vendorId,         /* store a PCI vendor ID */    UINT32  deviceId,         /* store a PCI device ID */    UINT8   revisionId        /* store a PCI revision ID */    )    {    UINT32  boardType;        /* store a BSP-specific board type constant */    UINT32  ioBase;           /* IO base address (BAR 0) */    UINT32  memIo32;          /* memory-mapped IO address (BAR 1) */    UINT8   irq;              /* interrupt line number (IRQ) for device */    /* number of physical units exceeded the number supported ? */    if (ln97XUnits >= LN97X_MAX_DEV)        {        return (ERROR);        }    if ((boardType = sysLn97xDev2Type (vendorId, deviceId, revisionId))        == BOARD_TYPE_UNKNOWN)        {        return (ERROR);        }    pciConfigInLong  (pciBus, pciDevice, pciFunc,                      PCI_CFG_BASE_ADDRESS_0, &ioBase);    pciConfigInLong  (pciBus, pciDevice, pciFunc,                      PCI_CFG_BASE_ADDRESS_1, &memIo32);    memIo32 &= PCI_MEMBASE_MASK;    ioBase  &= PCI_IOBASE_MASK;    /* map a 4Kb 32-bit non-prefetchable memory address decoder */    if (sysMmuMapAdd ((void *)(memIo32 & PCI_DEV_MMU_MSK),        PCI_DEV_ADRS_SIZE, VM_STATE_MASK_FOR_ALL, VM_STATE_FOR_PCI) == ERROR)        {        return (ERROR);        }    /* read the IRQ number and vector and save to the resource table */    pciConfigInByte (pciBus, pciDevice, pciFunc,                     PCI_CFG_DEV_INT_LINE, &irq);    /* update the board-specific resource table */    ln97xPciResources[ln97XUnits].bar[0]     = ioBase;    ln97xPciResources[ln97XUnits].bar[1]     = memIo32;    ln97xPciResources[ln97XUnits].irq        = irq;    ln97xPciResources[ln97XUnits].irqvec     = INT_NUM_GET (irq);    ln97xPciResources[ln97XUnits].vendorID   = vendorId;    ln97xPciResources[ln97XUnits].deviceID   = deviceId;    ln97xPciResources[ln97XUnits].revisionID = revisionId;    ln97xPciResources[ln97XUnits].boardType  = boardType;    /* enable mapped memory and IO decoders */    pciConfigOutWord (pciBus, pciDevice, pciFunc, PCI_CFG_COMMAND,                      PCI_CMD_MEM_ENABLE | PCI_CMD_IO_ENABLE |                      PCI_CMD_MASTER_ENABLE);    /* disable sleep mode */    pciConfigOutByte (pciBus, pciDevice, pciFunc, PCI_CFG_MODE,                      SLEEP_MODE_DIS);    ++ln97XUnits;  /* increment number of units initialized */    return (OK);    }/********************************************************************************* sysLan97xIntEnable - enable Am79C97x ethernet device interrupts** This routine enables Am79C97x interrupts.  This may involve operations on* interrupt control hardware.** RETURNS: OK or ERROR for invalid arguments.*/STATUS sysLan97xIntEnable    (    int level           /* level number */    )    {    return (sysIntEnablePIC (level));    }/********************************************************************************* sysLan97xIntDisable - disable Am79C97x ethernet device interrupts** This routine disables Am79C97x interrupts.  This may involve operations on* interrupt control hardware.** RETURNS: OK or ERROR for invalid arguments.*/STATUS sysLan97xIntDisable    (    int level           /* level number */    )    {    return (sysIntDisablePIC (level));    }/********************************************************************************* sysLan97xEnetAddrGet - get Am79C97x Ethernet (IEEE station) address** This routine provides a target-specific interface for accessing an* Am79C97x device Ethernet (IEEE station address) address in the device's* Address PROM (APROM).  A handle to the specific device control structure* is specified in the <pDrvCtrl> parameter.  The 6-byte IEEE station* address will be copied to the memory location specified by the* <enetAdrs> parameter.** INTERNAL* The 6 bytes of the IEEE station address occupy the first 6 locations of* the Address PROM space.  The driver must copy the station address from* the Address PROM space to the initialization block or to CSR12-14 in order* for the receiver to accept unicast frames directed to the device.** Bytes 14 and 15 of APROM should each be ASCII 'W' (57h).  The above* requirements must be met in order to be compatible with AMD driver* software.** The APROM is 32 bytes, and there is no need to read all of that here.* So, this routine reads half of the APROM to get the Ethernet address* and test for ASCII 'W's.** RETURNS: OK, or ERROR if could not be obtained.*/STATUS sysLan97xEnetAddrGet    (    LN_97X_DRV_CTRL *  pDrvCtrl,   /* Driver control */    char *             enetAdrs    )    {    char          aprom [LN_97X_APROM_SIZE];  /* copy of address PROM space */    int           numBytes = (LN_97X_APROM_SIZE >> 1);    register int  ix;    /* get IO address of unit */    UINT8 * const ioaddr = (UINT8 * const)(pDrvCtrl->devAdrs);    /* load APROM into an array */    if (pDrvCtrl->flags & LS_MODE_MEM_IO_MAP)        {        for (ix = 0; ix < numBytes; ++ix)            {            aprom[ix] = *(ioaddr + ix);            }        }    else        {        for (ix = 0; ix < numBytes; ++ix)            {            aprom[ix] = sysInByte ((int)(ioaddr + ix));            }        }    /* check for ASCII 'W's at APROM bytes 14 and 15 */    if ((aprom [0xe] != 'W') || (aprom [0xf] != 'W'))        {        logMsg ("sysLn97xEnetAddrGet:  W's not stored in aprom\n",                0, 1, 2, 3, 4, 5);        return ERROR;        }    bcopy (aprom, enetAdrs, 6);    return (OK);    }#endif /* INCLUDE_LN_97X_END */