/* sysGei82543End.c - Intel PRO1000X/F/XT/XF/MT/MF driver support routine *//* Copyright 1989-2002 Wind River Systems, Inc.  *//*modification history--------------------01j,07jul02,jln  add 82544GC device ID (spr#79520)01i,21may02,jln  support 82545/82546 fiber-based adapters (spr 78084)01h,25apr02,jln  fix short cable errata; support larger EEPROM; add more                  BSP specific functions; support 82540/82545/82546 chips;                  change the input argument of sys543IntEnable() and                  sys543IntDisable() from vector to unit.01g,23apr02,pai  Made DEC and GEI END driver config names consistent with                 other END driver config names.01f,05dec01,jln  save pciBus/pciDevice/pciFunc in pci resource table;                  more comments on PCI to PHY address translation01e,19nov01,pai  Pass the correct CSR memory size to sysMmuMapAdd().01d,09nov01,pai  Updated documentation and routines for new device discovery                 algorithm (SPR# 35716).01c,16Oct01,jln  added sysGei8254xEndLoad; refined device detecting01b,08Aug01,jln  support jumbo frame and 544_based adapter, more comments01a,08Jan01,jln  written based on sysNetif.c.*//*This module is the WRS-supplied configuration module for Intel PRO1000F/T/XF/XT/MT/MF adapters. It has routines for initializing device resourcesand provides BSP-specific gei82543End (gei) END driver routines forIntel 82540/3/4/5/6 Ethernet PCI bus controllers.The number of supported devices that can be configured for a particularsystem is finite and is specified by the GEI_MAX_DEV configurationconstant.  This value, and the internal data structures using it, can bemodified in this file for specific implementations.SEE ALSO: ifLib,.I "RS82543GC GIGABIT ETHERNET CONTROLLER NETWORKING SILICON DEVELOPER'S MANUAL"*/#if defined(INCLUDE_GEI8254X_END)/* namespace collisions */#undef INTEL_PCI_VENDOR_ID  /* redefined in gei82543End.h (temporary fix) *//* includes */#include "end.h"#include "drv/end/gei82543End.h"/* defines *//* specify the maximum number of physical devices to configure */#define GEI_MAX_DEV      (4)/* Default RX descriptor  */#ifndef GEI_RXDES_NUM#define GEI_RXDES_NUM              (GEI_DEFAULT_RXDES_NUM)#endif/* Default TX descriptor  */#ifndef GEI_TXDES_NUM#define GEI_TXDES_NUM              (GEI_DEFAULT_TXDES_NUM)#endif/* Default User's flags  *//* ORed the flag of GEI_END_JUMBO_FRAME_SUPPORT if jumbo frame needed */#ifndef GEI_USR_FLAG#define GEI_USR_FLAG        (GEI_END_SET_TIMER | \                             GEI_END_SET_RX_PRIORITY | \                             GEI_END_FREE_RESOURCE_DELAY \                            )#endif /* GEI_USR_FLAG *//*  * If jumbo frame supported, the default 9000 bytes of MTU will be used.  * Otherwise 1500 bytes MTU for normal frames. User can set up different  * MTU here for jumbo frames.  */#ifndef GEI_JUMBO_MTU_VALUE#define GEI_JUMBO_MTU_VALUE         (0)  /* Will use default value (9000) */#endif /* GEI_JUMBO_MTU_VALUE *//* * define the offset value for different arches. * For arch like ARM which requires 4-byte alignment for Integer,  * use offset of 2 */#define GEI_X86_OFFSET_VALUE        (0x0)#define GEI_ARM_OFFSET_VALUE        (0x2)#ifndef GEI_OFFSET_VALUE#define GEI_OFFSET_VALUE            GEI_X86_OFFSET_VALUE #endif /* GEI_OFFSET_VALUE *//* * Assuming Little-Endian Arch (i.e. swapping value for the Big-Endian Arch) */#define GEI_SYS_WRITE_REG(unit, reg, value)     \   ((*(volatile UINT32 *)(PCI_MEMIO2LOCAL(geiResources[(unit)].memBaseLow + reg))) = \    (UINT32)(value))#define GEI_SYS_READ_REG(unit, reg)             \   (*(volatile UINT32 *)(PCI_MEMIO2LOCAL(geiResources[(unit)].memBaseLow + reg)))/* PCI device ID for Intel 82543/82544 Ethernet */#define PRO1000_543_PCI_DEVICE_ID_T     (0x1001) /* Copper */#define PRO1000_543_PCI_DEVICE_ID_FT    (0x1004) /* Fiber / Copper */#define PRO1000_544_PCI_DEVICE_ID_XT    (0x1008) /* Copper */#define PRO1000_544_PCI_DEVICE_ID_XF    (0x1009) /* Fiber */#define PRO1000_544_PCI_DEVICE_ID_GC    (0x100c) /* Copper */#define PRO1000_540_PCI_DEVICE_ID_XT    (0x100e) /* Copper only */#define PRO1000_545_PCI_DEVICE_ID_XT    (0x100f) /* Copper */#define PRO1000_546_PCI_DEVICE_ID_XT    (0x1010) /* Copper */#define PRO1000_545_PCI_DEVICE_ID_MF    (0x1011) /* Fiber */#define PRO1000_546_PCI_DEVICE_ID_MF    (0x1012) /* Fiber *//* device resources */#define GEI_MEMSIZE_CSR            (0x20000)     /* 128Kb CSR memory size */#define GEI_MEMSIZE_FLASH          (0x80000)     /* 512Kb Flash memory size */#define GEI_EEPROM_SZ_64           (64)          /* 64 WORD */   #define GEI_EEPROM_SZ_256          (256)         /* 256 WORD */   #define GEI0_SHMEM_BASE             NONE#define GEI0_SHMEM_SIZE             (0)#define GEI0_RXDES_NUM              GEI_RXDES_NUM#define GEI0_TXDES_NUM              GEI_TXDES_NUM#define GEI0_USR_FLAG               GEI_USR_FLAG#define GEI1_SHMEM_BASE             NONE#define GEI1_SHMEM_SIZE             (0)#define GEI1_RXDES_NUM              GEI_RXDES_NUM#define GEI1_TXDES_NUM              GEI_TXDES_NUM#define GEI1_USR_FLAG               GEI_USR_FLAG#define GEI2_SHMEM_BASE             NONE#define GEI2_SHMEM_SIZE             (0)#define GEI2_RXDES_NUM              GEI_RXDES_NUM#define GEI2_TXDES_NUM              GEI_TXDES_NUM#define GEI2_USR_FLAG               GEI_USR_FLAG#define GEI3_SHMEM_BASE             NONE#define GEI3_SHMEM_SIZE             (0)#define GEI3_RXDES_NUM              GEI_RXDES_NUM#define GEI3_TXDES_NUM              GEI_TXDES_NUM#define GEI3_USR_FLAG               GEI_USR_FLAG/* INTEL 82544 INTERNAL PHY */#define INTEL_82544PHY_OUI_ID                   (0x5043)#define INTEL_82544PHY_MODEL                    (0x3)#define INTEL_82544PHY_PHY_SPEC_CTRL_REG        (0x10)#define INTEL_82544PHY_PHY_SPEC_STAT_REG        (0x11)#define INTEL_82544PHY_INT_ENABLE_REG           (0x12)#define INTEL_82544PHY_INT_STATUS_REG           (0x13)#define INTEL_82544PHY_EXT_PHY_SPEC_CTRL_REG    (0x14)#define INTEL_82544PHY_RX_ERROR_COUNTER         (0x15)#define INTEL_82544PHY_PHY_GLOBAL_STAT          (0x17)#define INTEL_82544PHY_LED_CTRL_REG             (0x18)#define INTEL_82544PHY_PSCR_ASSERT_CRS_ON_TX    (0x0800)#define INTEL_82544PHY_EPSCR_TX_CLK_25          (0x0070)/* Alaska PHY's information */#define MARVELL_OUI_ID                  (0x5043)#define MARVELL_ALASKA_88E1000          (0x5)#define MARVELL_ALASKA_88E1000S         (0x4)#define ALASKA_PHY_SPEC_CTRL_REG        (0x10)#define ALASKA_PHY_SPEC_STAT_REG        (0x11)#define ALASKA_INT_ENABLE_REG           (0x12)#define ALASKA_INT_STATUS_REG           (0x13)#define ALASKA_EXT_PHY_SPEC_CTRL_REG    (0x14)#define ALASKA_RX_ERROR_COUNTER         (0x15)#define ALASKA_LED_CTRL_REG             (0x18)#define ALASKA_PSCR_ASSERT_CRS_ON_TX    (0x0800)#define ALASKA_EPSCR_TX_CLK_25          (0x0070)#define ALASKA_PSCR_AUTO_X_1000T        (0x0040)#define ALASKA_PSCR_AUTO_X_MODE         (0x0060)#define ALASKA_PSSR_DPLX                (0x2000)#define ALASKA_PSSR_SPEED               (0xC000)#define ALASKA_PSSR_10MBS               (0x0000)#define ALASKA_PSSR_100MBS              (0x4000)#define ALASKA_PSSR_1000MBS             (0x8000)/* typedefs */typedef struct geiResource        /* GEI_RESOURCE */    {    BOOL   adr64;                 /* Indicator for 64-bit support */    UINT32 memBaseLow;            /* Base Address LOW */    UINT32 memBaseHigh;           /* Base Address HIGH */    UINT32 flashBase;             /* Base Address for FLASH */    UINT16 eepromSize;            /* size in unit of word (16 bit) - 64/256 */     UINT16 eeprom_icw1;           /* EEPROM initialization control word 1 */    UINT16 eeprom_icw2;           /* EEPROM initialization control word 2 */    UCHAR  enetAddr[6];           /* MAC address for this adaptor */    UINT32 shMemBase;             /* Share memory address if any */    UINT32 shMemSize;             /* Share memory size if any */    UINT32 rxDesNum;              /* RX descriptor for this unit */    UINT32 txDesNum;              /* TX descriptor for this unit */    BOOL   useShortCable;         /* TRUE if short cable used for 82544 */                                     /* by default is FALSE */    UINT32 usrFlags;              /* user flags for this unit */    STATUS iniStatus;             /* initialization perform status */    } GEI_RESOURCE;/* locals */LOCAL UINT32 geiUnits = 0;     /* number of GEIs we found *//* This table defined board extended resources */LOCAL GEI_RESOURCE geiResources [GEI_MAX_DEV] =    {    {FALSE, NONE, NONE, NONE, GEI_EEPROM_SZ_64, 0, 0, {NONE},     GEI0_SHMEM_BASE, GEI0_SHMEM_SIZE, GEI0_RXDES_NUM, GEI0_TXDES_NUM, FALSE,      GEI0_USR_FLAG, ERROR    },    {FALSE, NONE, NONE, NONE, GEI_EEPROM_SZ_64, 0, 0, {NONE},     GEI1_SHMEM_BASE, GEI1_SHMEM_SIZE, GEI1_RXDES_NUM, GEI1_TXDES_NUM, FALSE,      GEI1_USR_FLAG, ERROR    },    {FALSE, NONE, NONE, NONE, GEI_EEPROM_SZ_64, 0, 0, {NONE},     GEI2_SHMEM_BASE, GEI2_SHMEM_SIZE, GEI2_RXDES_NUM, GEI2_TXDES_NUM, FALSE,      GEI2_USR_FLAG, ERROR    },    {FALSE, NONE, NONE, NONE, GEI_EEPROM_SZ_64, 0, 0, {NONE},     GEI3_SHMEM_BASE, GEI3_SHMEM_SIZE, GEI3_RXDES_NUM, GEI3_TXDES_NUM, FALSE,      GEI3_USR_FLAG, ERROR    }    };/* This table defines board PCI resources */LOCAL PCI_BOARD_RESOURCE geiPciResources [GEI_MAX_DEV] =    {    {NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE,    {NONE, NONE, NONE, NONE, NONE, NONE},     (void * const)(&geiResources[0])    },    {NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE,    {NONE, NONE, NONE, NONE, NONE, NONE},     (void * const)(&geiResources[1])    },    {NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE,    {NONE, NONE, NONE, NONE, NONE, NONE},     (void * const)(&geiResources[2])    },    {NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE, NONE,    {NONE, NONE, NONE, NONE, NONE, NONE},     (void * const)(&geiResources[3])    }    };/* forward declarations */LOCAL int       sys543IntEnable  (int unit);LOCAL int       sys543IntDisable (int unit);LOCAL int       sys543IntAck     (int unit);LOCAL STATUS    sys543eepromCheckSum (int unit);LOCAL UINT16    sys543eepromReadWord (int unit,UINT32);LOCAL STATUS    sys543EtherAdrGet (int unit);LOCAL void      sys544PhyPreInit (PHY_INFO *);LOCAL void      sys543PhySpecRegsInit(PHY_INFO *, UINT8);LOCAL BOOL      sysGei82546InitTimerSetup (ADAPTOR_INFO * ); LOCAL BOOL      sysGei82546DynaTimerSetup (ADAPTOR_INFO * ); LOCAL UINT32    sysGeiDevToType (UINT32, UINT32, UINT8);/******************************************************************************* sys543PciInit - initialize a GEI 8254x PCI ethernet device** This routine performs basic PCI initialization for 8254x ethernet* devices supported by the gei82543End END driver.  Parameters to this* routine specify a PCI function, including PCI ID registers, to* initialize.  If supported,  the device memory and I/O addresses are* mapped into the local CPU address space and an internal board-specific* PCI resources table is updated with information on the board type,* memory address, and IO address.** CAVEATS* This routine must be performed prior to MMU initialization, usrMmuInit().* If the number of supported 8254x physical device instances installed* on the PCI bus exceeds GEI_MAX_DEV, then the extra devices will not be* initialized in this routine.** RETURNS:* OK, or ERROR if the specified device is not supported, or if* the device could not be mapped into the local CPU memory space.*/STATUS sys543PciInit    (    UINT32         pciBus,      /* store a PCI bus number */    UINT32         pciDevice,   /* store a PCI device number */    UINT32         pciFunc,     /* store a PCI function number */    UINT32         vendorId,    /* store a PCI vendor ID */    UINT32         deviceId,    /* store a PCI device ID */    UINT8          revisionId   /* store a PCI revision ID */    )    {    UINT32         boardType;   /* store a BSP-specific board type constant */    UINT32         memBaseLo;   /* temporary BAR storage */    UINT32         memBaseHi;    UINT32         flashBase;    UINT8          irq;         /* store PCI interrupt line (IRQ) number */    GEI_RESOURCE * pReso;       /* alias extended resource table */    /* number of physical units exceeded the number supported ? */    if (geiUnits >= GEI_MAX_DEV)        {        return (ERROR);        }    if ((boardType = sysGeiDevToType (vendorId, deviceId, revisionId))        == BOARD_TYPE_UNKNOWN)        {        return (ERROR);        }    /* BAR information will be saved in the extended resource table */    pReso = (GEI_RESOURCE *)(geiPciResources[geiUnits].pExtended);    /*     * BAR0: [32:17]: memory base     *       [16:4] : read as "0";     *       [3]    : 0 - device is not prefetchable     *       [2:1]  : 00b - 32-bit address space, or     *                01b - 64-bit address space     *       [0]    : 0 - memory map decoded     *     * BAR1: if BAR0[2:1] == 00b, optional flash memory base     *       if BAR0[2:1] == 01b, high portion of memory base      *                            for 64-bit address space