case WINDML_AUDIO_DEVICE:            {            if ((vendorID == 0) && (deviceID == 0))                {                /* If there are no PCI audio class devices ... */                if (pciMmAudioDevNo == 0)                    {                    return (pDev);                    }                else if ((instance >= 0) && (instance < pciMmAudioDevNo))                    {                    return (pciMmAudioDevs[instance]);                    }                }            else if (deviceID == 0)                {                /* Find the specified <instance> of the specified PCI                 * <vendorID> value.                 */                int i;                for (i = 0; i < pciMmAudioDevNo; ++i)                    {                    if (((pciMmAudioDevs[i])->vendorID == vendorID) &&                        (instance-- == 0))                        {                        return (pciMmAudioDevs[i]);                        }                    }                }            else                {                /* Find the specified <instance> of the specified PCI                 * <vendorID> and <deviceID> values.                 */                int i;                for (i = 0; i < pciMmAudioDevNo; ++i)                    {                    if (((pciMmAudioDevs[i])->vendorID == vendorID) &&                        ((pciMmAudioDevs[i])->deviceID == deviceID) &&                        (instance-- == 0))                        {                        return (pciMmAudioDevs[i]);                        }                    }                }            break;            }        }    return (pDev);    }/********************************************************************************* sysWindMLDevCtrl - special control of the device mode** This routine provides special control features for the device.  This* function is essentially a catch all to provide control of the device* where the functionality is provided within a PCI configuration header or* by board specific registers which may be shared by other functions* implemented on the target board.** The <function> argument defines the type of function that is to be* performed and the <pArg> parameter provides the details relating to the* function. ** The values for <function> and the interpretation of the <pArg> parameters* are:**\is*\i WINDML_ACCESS_MODE_SET*       Sets the device's access mode as to whether it is to respond to I/O*       cycles of memory mapped cycles or both.  The accessibility is*       provided by the <pArg> parameter which is bit mapped containing the*       flags WINDML_MEM_ENABLE (enable memory mapped access) and*       WINDML_IO_ENABLE (enable I/O access).*\i WINDML_LCD_MODE_SET*       Sets the control mode for an LCD that is controllable by an on board*       register rather than a graphics device register. The mode information*       is passed through <pArg>. The flags available are WINDML_LCD_ON*       WINDML_LCD_OFF, WINDML_BACKLIGHT_ON, WINDML_BACKLIGHT_OFF.*\i WINDML_BUSWIDTH_SET*       Some boards allow the LCD bus width to be changed dynamically via*       an FPGA or other configurable logic. This can be done in a board*       specific manner. The actual bus width will be passed through <pArg>.*\i WINDML_PCI_MEMBASE_GET*       Obtain the base address of CPU memory as seen by PCI devices.  *\ie** RETURNS: OK for successful control operations, else ERROR.*/STATUS sysWindMLDevCtrl     (    WINDML_DEVICE * pDev,        /* Device to control */    int             function,    /* Type of operation to perform */    int *           pArg         /* Control mode */    )    {    STATUS status = ERROR;    if (pDev == NULL)        {        return (status);        }    switch (function)        {        /* Conrol the PCI access mode, the command byte */        case WINDML_ACCESS_MODE_SET:            {            int busno, devno, funcno;            if (pciFindDevice (pDev->vendorID,                               pDev->deviceID,                               pDev->instance,                                &busno, &devno, &funcno) != OK)                {                return (ERROR);                }            status = pciConfigOutWord (busno, devno, funcno,                                       PCI_CFG_COMMAND, *pArg);            break;            }        /* Obtain the CPU memory base address as seen by PCI device */        case WINDML_PCI_MEMBASE_GET:            /* PCI memory base is same as CPU, so set to 0 */            *pArg = 0;            break;        }    return (status);    }/********************************************************************************* sysWindMLDevRelease - release a device configuration** This routine will release any resources that were allocated when a  * device was configured using the sysWindMLDevGet() function.  This * function will free the memory that was allocated for the WINDML_DEVICE * data structure if it was dynamically allocated.  If the data structure* was not dynamically allocated, this function will usually be simply a* stub.** INTERNAL* When a static memory pool configuration is used, <pDev> descriptors* for PCI devices are not released back to the static pool once they* are successfully allocated and initialized at the conclusion of the* sysWindMLHwInit() routine.** RETURNS: OK for a successful release operation, else ERROR.*/STATUS sysWindMLDevRelease     (    WINDML_DEVICE * pDev         /* Device to release */    )    {#ifdef    SYS_WINDML_STATIC_MEM_POOL    if ((pDev != NULL) && (pDev->busType != BUS_TYPE_PCI))        {        sysWindMlDescFree (pDev);        }#else    if (pDev != NULL)        {        sysWindMlDescFree (pDev);        }#endif /* SYS_WINDML_STATIC_MEM_POOL */    return (OK);    }/********************************************************************************* sysWindMLIntConnect - Connect the device interrupt** This routine connects a routine to the interrupt.** RETURNS: OK or ERROR.*/STATUS sysWindMLIntConnect    (    WINDML_DEVICE * pDev,        /* Graphics device to control */    VOIDFUNCPTR     routine,     /* routine to be called */    int             parameter    /* parameter to be passed */    )    {    STATUS status = ERROR;    if ((pDev != NULL) && (pDev->intVector != NULL) && (routine != NULL))        {        if (pDev->busType == BUS_TYPE_PCI)            status = pciIntConnect (pDev->intVector, routine, parameter);        else            status = intConnect (pDev->intVector, routine, parameter);        }    return (status);    }/********************************************************************************* sysWindMLIntEnable - Enable interrupts** This routine enables the interrupt.** RETURNS: OK or ERROR.*/STATUS sysWindMLIntEnable    (    WINDML_DEVICE * pDev         /* Device to control */    )    {    return ((pDev != NULL) ? (sysIntEnablePIC (pDev->intLevel)) : (ERROR));    }/********************************************************************************* sysWindMLIntDisable - Disable interrupts** This routine disables the interrupt.** RETURNS: OK or ERROR.*/STATUS sysWindMLIntDisable    (    WINDML_DEVICE * pDev         /* Device to control */    )    {    return ((pDev != NULL) ? (sysIntDisablePIC (pDev->intLevel)) : (ERROR));    }/********************************************************************************* sysWindMlPciDevMap - map a WindML device into the host address space** This routine initializes the <pPhysBaseAdrs(n)> fields of the specified* WINDML_DEVICE descriptor with the PCI base address register (BAR) values* from a PCI device specified by <bus>, <dev>, and <func>.  The WindML* device's PCI memory decoders, if any, are mapped into the host processor's* address space.** CAVEATS* As of PCI 2.2, decoders may be implemented in any of the base address* register (BAR) positions.  If more than one decoder is implemented,* there may be holes.  Therefore, inspect all six of the possible BAR* positions in the device header to determine which registers are actually* implemented.** This routine will not correctly detect and handle 64-bit base address* registers.** The BSP-specific sysMmuMapAdd() routine is used to create <sysPhysMemDesc>* table entries for memory BARs.  As a result, this routine should be used* _before_ the <sysPhysMemDesc> table is referenced for the purpose of* initializing the MMU or processor address space (us. in usrMmuInit()).** All memory BARs will be mapped as uncacheable, regardless of whether the* Prefetchable Attribute Bit is set in the BAR.  This has been done for* the following reasons:**     (1) The WindML graphics drivers do not manually flush and / or*         invalidate R/W transactions to things like frame buffers.**     (2) Some supported devices are known to set the Prefetchable bit*         in memory BARs for memory regions in which the device implements*         memory-mapped I/O registers.  This is not "the right thing" for*         the device to do, but it is a reality that we have to deal with.** RETURNS:* OK, else ERROR if memory decoders could not be mapped into the processor's* address space.  In the case of an ERROR return, the <pPhysBaseAdrs> fields* of the specified WINDML_DEVICE are undefined.** NOMANUAL*/LOCAL STATUS sysWindMlPciDevMap    (    WINDML_DEVICE * pDev,       /* WindML device descriptor */    UINT32          bus,        /* device's PCI bus number */    UINT32          dev,        /* device's PCI device number */    UINT32          func        /* device's PCI function number */    )    {    UINT16          cmdSave;    /* saves 16-bit PCI command word register */    UINT32          barSave;    /* saves 32-bit PCI base address register */    UINT32          barRead;    /* memory decoder (if any) read from BAR  */    STATUS          retVal = OK;    /* save PCI device command word register & disable memory decode */    pciConfigInWord  (bus, dev, func, PCI_CFG_COMMAND, &cmdSave);    pciConfigOutWord (bus, dev, func, PCI_CFG_COMMAND,                      cmdSave & ((~PCI_CMD_MEM_ENABLE) | (~PCI_CMD_IO_ENABLE)));    /* save the BARs and determine whether memory decoders are implemented */    pciConfigInLong  (bus, dev, func, PCI_CFG_BASE_ADDRESS_0, &barSave);    pDev->pPhysBaseAdrs0 = (void *) barSave;    pciConfigOutLong (bus, dev, func, PCI_CFG_BASE_ADDRESS_0, 0xffffffff);    pciConfigInLong  (bus, dev, func, PCI_CFG_BASE_ADDRESS_0, &barRead);    if (barRead != 0)        {        pciConfigOutLong (bus, dev, func, PCI_CFG_BASE_ADDRESS_0, barSave);        if ((barRead & PCI_BASE_IO) != PCI_BAR_SPACE_IO)            {            barSave  &= PCI_MEMBASE_MASK;            barRead  &= PCI_MEMBASE_MASK;            if (sysMmuMapAdd ((void *) barSave, (1 << (ffsLsb (barRead) - 1)),                VM_STATE_MASK_FOR_ALL, VM_STATE_FOR_IO) == ERROR)                {                retVal = ERROR;                goto WINDML_MAP_DEV_RETURN;                }            }        }    pciConfigInLong  (bus, dev, func, PCI_CFG_BASE_ADDRESS_1, &barSave);    pDev->pPhysBaseAdrs1 = (void *) barSave;    pciConfigOutLong (bus, dev, func, PCI_CFG_BASE_ADDRESS_1, 0xffffffff);    pciConfigInLong  (bus, dev, func, PCI_CFG_BASE_ADDRESS_1, &barRead);    if (barRead != 0)        {        pciConfigOutLong (bus, dev, func, PCI_CFG_BASE_ADDRESS_1, barSave);        if ((barRead & PCI_BASE_IO) != PCI_BAR_SPACE_IO)            {            barSave  &= PCI_MEMBASE_MASK;            barRead  &= PCI_MEMBASE_MASK;            if (sysMmuMapAdd ((void *) barSave, (1 << (ffsLsb (barRead) - 1)),                VM_STATE_MASK_FOR_ALL, VM_STATE_FOR_IO) == ERROR)                {                retVal = ERROR;                goto WINDML_MAP_DEV_RETURN;                }            }