#======================================================## Synopsys Synthesis Scripts (Design Vision dctcl mode)##======================================================#======================================================#  Set Libraries#======================================================set search_path {. ./ \                   ~iclabt01/UMC018_LIB/Synthesis \                   /usr/synopsys/libraries/syn/ }#                   /misc/RAID2/EDA/synopsys/syn_vV-2004.06-SP1/libraries/syn }set link_library {* slow.db dw01.sldb dw02.sldb dw03.sldb dw04.sldb dw05.sldb}set synthetic_library {standard.sldb dw01.sldb dw02.sldb dw03.sldb dw04.sldb dw05.sldb}set target_library {slow.db}#======================================================#  Global Parameters#======================================================set DESIGN "TRIANGLE"set CLK_period 10set MAX_Delay 10 #======================================================#  Read RTL Code#======================================================read_verilog -rtl $DESIGN\.vcurrent_design $DESIGN#======================================================#  Global Setting#======================================================#======================================================#  Set Design Constraints#======================================================set_max_delay $MAX_Delay -from [all_inputs] -to [all_outputs]#======================================================#  Optimization#======================================================uniquifyset_fix_multiple_port_nets -all -buffer_constantscompile_ultra#======================================================#  Output Reports #======================================================report_timing >  $DESIGN\.timingreport_area >  $DESIGN\.area#======================================================#  Change Naming Rule#======================================================set bus_inference_style "%s\[%d\]"set bus_naming_style "%s\[%d\]"set hdlout_internal_busses truechange_names -hierarchy -rule verilogdefine_name_rules name_rule -allowed "a-z A-Z 0-9 _" -max_length 255 -type celldefine_name_rules name_rule -allowed "a-z A-Z 0-9 _[]" -max_length 255 -type netdefine_name_rules name_rule -map {{"\\*cell\\*" "cell"}}change_names -hierarchy -rules name_rule#======================================================#  Output Results#======================================================set verilogout_higher_designs_first truewrite -format verilog -output $DESIGN\_SYN.v -hierarchywrite_sdf -version 2.1 -context verilog -load_delay cell $DESIGN\_SYN.sdf#======================================================#  Finish and Quit#======================================================exit