library verilog;use verilog.vl_types.all;entity wallace_tree is    port(        \OUT\           : out    vl_logic_vector(26 downto 0);        p1              : in     vl_logic_vector(26 downto 0);        p2              : in     vl_logic_vector(26 downto 0);        p3              : in     vl_logic_vector(26 downto 0);        p4              : in     vl_logic_vector(26 downto 0);        p5              : in     vl_logic_vector(26 downto 0);        p6              : in     vl_logic_vector(26 downto 0);        p7              : in     vl_logic_vector(26 downto 0)    );end wallace_tree;