library verilog;use verilog.vl_types.all;entity booth is    port(        p               : out    vl_logic_vector(26 downto 0);        y_0             : in     vl_logic;        y_1             : in     vl_logic;        y_2             : in     vl_logic;        x_1             : in     vl_logic_vector(26 downto 0)    );end booth;