?? _primary.vhd
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library verilog;use verilog.vl_types.all;entity triangle is port( area : out vl_logic_vector(26 downto 0); ax : in vl_logic_vector(11 downto 0); ay : in vl_logic_vector(11 downto 0); bx : in vl_logic_vector(11 downto 0); by : in vl_logic_vector(11 downto 0); cx : in vl_logic_vector(11 downto 0); cy : in vl_logic_vector(11 downto 0) );end triangle;
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