;define the stack size
SVC_STACK_LEGTH         EQU         0
FIQ_STACK_LEGTH         EQU         0
IRQ_STACK_LEGTH         EQU         256
ABT_STACK_LEGTH         EQU         0
UND_STACK_LEGTH         EQU         0

NoInt       EQU 0x80
NoFIQ		EQU	0x40   


USR32Mode   EQU 0x10
SVC32Mode   EQU 0x13
SYS32Mode   EQU 0x1f
IRQ32Mode   EQU 0x12
FIQ32Mode   EQU 0x11

PINSEL2     EQU 0xE002C014

;/* Define the Bus Speed */
BCFG0       EQU     0xFFE00000      ;// Control Word of BANK0 / CS0
BCFG1       EQU     0xFFE00004      ;// Control Word of BANK1 / CS1
BCFG2       EQU     0xFFE00008      ;// Control Word of BANK2 / CS2
BCFG3       EQU     0xFFE0000C      ;// Control Word of BANK3 / CS3

BCFG_08DEF	EQU	    0x00000000      ;//  8Bit Bus
BCFG_16DEF	EQU	    0x10000400      ;// 16Bit Bus
BCFG_32DEF	EQU	    0x20000400      ;// 32Bit Bus


BCFG_FLASH	EQU		(BCFG_16DEF | (0x00<<00) | (0x03<<05) | (0x02<<11))   ;// For 90ns Flash
BCFG_PSRAM  EQU		(BCFG_16DEF | (0x00<<00) | (0x03<<05) | (0x02<<11))   ;// For 70ns PSRAM
BCFG_CS2	EQU		(BCFG_16DEF | (0x0f<<00) | (0x1f<<05) | (0x1f<<11))   ;// Blank 
BCFG_CS3    EQU		(BCFG_16DEF | (0x01<<00) | (0x03<<05) | (0x03<<11))   ;// For Peripheral Equipment

    IMPORT __use_no_semihosting_swi
    IMPORT __use_two_region_memory



    IMPORT  FIQ_Exception                   
    IMPORT  __main                         
    IMPORT  TargetResetInit             


    EXPORT  bottom_of_heap
    EXPORT  bottom_of_Stacks
    EXPORT  top_of_heap
    EXPORT  StackUsr
    
    EXPORT  Reset
    EXPORT __user_initial_stackheap

    CODE32
	PRESERVE8
    AREA    vectors,CODE,READONLY
        ENTRY

;interrupt vectors
Reset
        LDR     PC, ResetAddr
        LDR     PC, UndefinedAddr
        LDR     PC, SWI_Addr
        LDR     PC, PrefetchAddr
        LDR     PC, DataAbortAddr
        DCD     0xb9205f80
        LDR     PC, [PC, #-0xff0]
        LDR     PC, FIQ_Addr

ResetAddr           DCD     ResetInit
UndefinedAddr       DCD     Undefined
SWI_Addr            DCD     SoftwareInterrupt
PrefetchAddr        DCD     PrefetchAbort
DataAbortAddr       DCD     DataAbort
Nouse               DCD     0
IRQ_Addr            DCD     0
FIQ_Addr            DCD     FIQ_Handler


Undefined
        B       Undefined

SoftwareInterrupt			
;        B       SoftwareInterrupt
                           
        CMP     R0, #4
        LDRLO   PC, [PC, R0, LSL #2]
        MOVS    PC, LR

SwiFunction
        DCD     IRQDisable       ;0
        DCD     IRQEnable        ;1
        DCD		FIQDisable		 ;2
        DCD		FIQEnable		 ;3

IRQDisable
        
        MRS     R0, SPSR
        ORR     R0, R0, #NoInt
        MSR     SPSR_c, R0
        MOVS    PC, LR

IRQEnable
        
        MRS   R0, SPSR
        BIC   R0, R0, #NoInt
        MSR   SPSR_c, R0
        MOVS    PC, LR
        
FIQDisable
       
        MRS     R0, SPSR
        ORR     R0, R0, #NoFIQ
        MSR     SPSR_c, R0
        MOVS    PC, LR

FIQEnable
       
        MRS   R0, SPSR
        BIC   R0, R0, #NoFIQ
        MSR   SPSR_c, R0
        MOVS    PC, LR



PrefetchAbort
        B       PrefetchAbort


DataAbort
        B       DataAbort


FIQ_Handler
        STMFD   SP!, {R0-R3, LR}
        BL      FIQ_Exception
        LDMFD   SP!, {R0-R3, LR}
        SUBS    PC,  LR,  #4

InitStack    
        MOV     R0, LR
;Build the SVC stack
        MSR     CPSR_c, #0xd3		
        LDR     SP, StackSvc
;Build the IRQ stack			
        MSR     CPSR_c, #0xd2
        LDR     SP, StackIrq
;Build the FIQ stack
        MSR     CPSR_c, #0xd1
        LDR     SP, StackFiq
;Build the DATAABORT stack
        MSR     CPSR_c, #0xd7
        LDR     SP, StackAbt
;Build the UDF stack
        MSR     CPSR_c, #0xdb
        LDR     SP, StackUnd
;Build the SYS stack
        MSR     CPSR_c, #0xdf
        LDR     SP, =StackUsr

        BX			R0

ResetInit
;Initial extenal bus controller.

        LDR     R0, =PINSEL2
    IF :DEF: EN_CRP
        LDR     R1, =0x0f814910
    ELSE
        LDR     R1, =0x0f814914
    ENDIF
        STR     R1, [R0]
        
        LDR     R0, =BCFG0
        LDR     R1, =BCFG_FLASH
        STR     R1, [R0]

        LDR     R0, =BCFG1
        LDR     R1, =BCFG_PSRAM
        STR     R1, [R0]

        LDR     R0, =BCFG2
        LDR     R1, =BCFG_CS2
        STR     R1, [R0]

        LDR     R0, =BCFG3
        LDR     R1, =BCFG_CS3
        STR     R1, [R0]
        
        BL      InitStack               ;Initialize the stack
        BL      TargetResetInit         ;Initialize the target board
                                        ;Jump to the entry point of C program
        B       __main


__user_initial_stackheap    
    LDR   r0,=bottom_of_heap
;    LDR   r1,=StackUsr
    LDR   r2,=top_of_heap
    LDR   r3,=bottom_of_Stacks
    BX		lr


StackSvc           DCD     SvcStackSpace + (SVC_STACK_LEGTH - 1)* 4
StackIrq           DCD     IrqStackSpace + (IRQ_STACK_LEGTH - 1)* 4
StackFiq           DCD     FiqStackSpace + (FIQ_STACK_LEGTH - 1)* 4
StackAbt           DCD     AbtStackSpace + (ABT_STACK_LEGTH - 1)* 4
StackUnd           DCD     UndtStackSpace + (UND_STACK_LEGTH - 1)* 4

    IF :DEF: EN_CRP
        IF  . >= 0x1fc
        INFO    1,"\nThe data at 0x000001fc must be 0x87654321.\nPlease delete some source before this line."
        ENDIF
CrpData
    WHILE . < 0x1fc
    NOP
    WEND
CrpData1
    DCD     0x87654321          ;/*When the Data is 0x87654321,user code be protected. */
    ENDIF
    

        AREA    MyStacks, DATA, NOINIT, ALIGN=2
SvcStackSpace      SPACE   SVC_STACK_LEGTH * 4  
IrqStackSpace      SPACE   IRQ_STACK_LEGTH * 4  
FiqStackSpace      SPACE   FIQ_STACK_LEGTH * 4  ;Stack spaces for Fast Interrupt reQuest Mode 
AbtStackSpace      SPACE   ABT_STACK_LEGTH * 4  ;Stack spaces for Suspend Mode 
UndtStackSpace     SPACE   UND_STACK_LEGTH * 4  ;Stack spaces for Undefined Mode 


        AREA    Heap, DATA, NOINIT
bottom_of_heap    SPACE   1

        AREA    StackBottom, DATA, NOINIT
bottom_of_Stacks    SPACE   1

        AREA    HeapTop, DATA, NOINIT
top_of_heap

        AREA    Stacks, DATA, NOINIT
StackUsr

    END