{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 08 11:20:18 2008 " "Info: Processing started: Sat Nov 08 11:20:18 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off bj -c bj --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off bj -c bj --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 6 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register cur_state.s3 cur_state.s0 405.19 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 405.19 MHz between source register \"cur_state.s3\" and destination register \"cur_state.s0\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "1.234 ns 1.234 ns 2.468 ns " "Info: fmax restricted to Clock High delay (1.234 ns) plus Clock Low delay (1.234 ns) : restricted to 2.468 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.882 ns + Longest register register " "Info: + Longest register to register delay is 0.882 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cur_state.s3 1 REG LC_X2_Y20_N0 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y20_N0; Fanout = 3; REG Node = 'cur_state.s3'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { cur_state.s3 } "NODE_NAME" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.467 ns) 0.882 ns cur_state.s0 2 REG LC_X2_Y20_N5 3 " "Info: 2: + IC(0.415 ns) + CELL(0.467 ns) = 0.882 ns; Loc. = LC_X2_Y20_N5; Fanout = 3; REG Node = 'cur_state.s0'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.882 ns" { cur_state.s3 cur_state.s0 } "NODE_NAME" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.467 ns ( 52.95 % ) " "Info: Total cell delay = 0.467 ns ( 52.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.415 ns ( 47.05 % ) " "Info: Total interconnect delay = 0.415 ns ( 47.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.882 ns" { cur_state.s3 cur_state.s0 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "0.882 ns" { cur_state.s3 {} cur_state.s0 {} } { 0.000ns 0.415ns } { 0.000ns 0.467ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.271 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 4 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.594 ns) + CELL(0.547 ns) 2.271 ns cur_state.s0 2 REG LC_X2_Y20_N5 3 " "Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X2_Y20_N5; Fanout = 3; REG Node = 'cur_state.s0'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.141 ns" { clk cur_state.s0 } "NODE_NAME" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 73.84 % ) " "Info: Total cell delay = 1.677 ns ( 73.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.594 ns ( 26.16 % ) " "Info: Total interconnect delay = 0.594 ns ( 26.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { clk cur_state.s0 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { clk {} clk~out0 {} cur_state.s0 {} } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.271 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 4 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 4; CLK Node = 'clk'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.594 ns) + CELL(0.547 ns) 2.271 ns cur_state.s3 2 REG LC_X2_Y20_N0 3 " "Info: 2: + IC(0.594 ns) + CELL(0.547 ns) = 2.271 ns; Loc. = LC_X2_Y20_N0; Fanout = 3; REG Node = 'cur_state.s3'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.141 ns" { clk cur_state.s3 } "NODE_NAME" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 73.84 % ) " "Info: Total cell delay = 1.677 ns ( 73.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.594 ns ( 26.16 % ) " "Info: Total interconnect delay = 0.594 ns ( 26.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { clk cur_state.s3 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { clk {} clk~out0 {} cur_state.s3 {} } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { clk cur_state.s0 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { clk {} clk~out0 {} cur_state.s0 {} } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { clk cur_state.s3 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { clk {} clk~out0 {} cur_state.s3 {} } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.882 ns" { cur_state.s3 cur_state.s0 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "0.882 ns" { cur_state.s3 {} cur_state.s0 {} } { 0.000ns 0.415ns } { 0.000ns 0.467ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { clk cur_state.s0 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { clk {} clk~out0 {} cur_state.s0 {} } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.271 ns" { clk cur_state.s3 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.271 ns" { clk {} clk~out0 {} cur_state.s3 {} } { 0.000ns 0.000ns 0.594ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { cur_state.s0 } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { cur_state.s0 {} } {  } {  } "" } } { "bj.vhd" "" { Text "E:/QuartueII/bj/bj.vhd" 12 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}