#define  BIT( n )				( 1 << n )
//USB
#define Usb_read_byte()            (UEPDATX)
#define Usb_write_byte(x)         (UEPDATX = x)
#define SelectEndpoint(n)    	   UEPNUM=n&0x02
#define Usb_clear_TXCMPL()      (UEPSTAX &= ~0x01)   	
#define Usb_clear_RXOUT_PP()   {if(rx_bank){UEPSTAX&=~0x40;}else{UEPSTAX&=(~0x02);}rx_bank=~rx_bank;}
#define Disable_Boot_Flash()      AUXR1&=~bit5;
#define Usb_tx_complete_bit()   (UEPSTAX & 0x01)

//ATA
#define Set_Adr_DRV_HEAD()         {CS1=1;CS0=0;DA2=1;DA1=1;DA0=0;}
#define Set_Adr_COMMAND()          {CS1=1;CS0=0;DA2=1;DA1=1;DA0=1;}         
#define Set_Adr_DEV_CTR()            {CS1=0;CS0=1;DA2=1;DA1=1;DA0=0;}
#define Set_Adr_CYL()                   {CS1=1;CS0=0;DA2=1;DA1=0;DA0=0;}
#define Set_Adr_CYH()                   {CS1=1;CS0=0;DA2=1;DA1=0;DA0=1;}
#define Set_Adr_SN()                     {CS1=1;CS0=0;DA2=0;DA1=1;DA0=1;}
#define Set_Adr_SC()                     {CS1=1;CS0=0;DA2=0;DA1=1;DA0=0;}
#define Set_Adr_STATUS()              {CS1=1;CS0=0;DA2=1;DA1=1;DA0=1;}
#define Set_Adr_ALT_STATUS()       {CS1=0;CS0=1;DA2=1;DA1=1;DA0=0;}
#define Set_Adr_DATA()                 {CS1=1;CS0=0;DA2=0;DA1=0;DA0=0;}




#define SMOD1()		                    PCON|=0x80;
////////////////////////2007////////////////////
#define Set_x2_mode()                  (CKCON |= 0x01)
#define Enable_interrupt()      (EA = 1)
#define Disable_interrupt()     (EA = 0)


/* for PLL macro*/
#define Pll_reset()                    (PLLCON &= 0x08) 
#define Pll_enable()                  (PLLCON |= 0x02) 
#define Pll_stop()                     (PLLCON &= ~0x02)
#define Pll_ndiv(n)                   (PLLNDIV = n)
#define Pll_rdiv(r)                    (PLLRDIV = (UINT8)(r >> 2)); (PLLCON = (UINT8)(r << 6))
#define Set_Usb_clock(clk)       (USBCLK = clk)
#define Usb_enable()               (USBCON |= 0x80)
#define Reset_All_Ep()             (UEPRST = 0x07)
#define Stop_Reset_All_Ep()    (UEPRST = 0x00)
#define Usb_sel_ep(ep)           (UEPNUM = ep)
#define Usb_suspend()            (USBINT & 0x01)
#define Usb_resume()             (USBINT & 0x20)
#define Usb_reset_event()                 (USBINT & 0x10)
#define Clear_Usb_reset_event()        (USBINT &= ~0x10)
#define Usb_ep_int_event()                 (UEPINT)
#define Usb_setup_packet_receive()          (UEPSTAX & 0x04)
#define Usb_set_DIR_bit()                 (UEPSTAX |= 0x80)
#define Usb_clr_rxsetup_bit()           (UEPSTAX &= ~0x04)
#define Usb_set_TXRDY_bit()               (UEPSTAX |= 0x10)
#define Usb_receive_out_data()             (UEPSTAX & 0x42)
#define Usb_send_data_complete()             (UEPSTAX & 0x01)
#define Usb_clear_RXOUTB0_bit()             (UEPSTAX &= ~0x02)
#define Usb_clear_TXCMPL_bit()            (UEPSTAX &= ~0x01)
#define Usb_clear_DIR_bit()               (UEPSTAX &= ~0x80)
#define Usb_set_FADDEN_bit()              (USBCON |= 0x01)
#define Usb_set_USBADDR(x)      (USBADDR = (0x80 | x))
#define Usb_set_CONFG()               (USBCON |= 0x02)
#define Usb_clear_CONFG()             (USBCON &= ~0x02)
#define Usb_ep_enable()                 (UEPCONX |= 0x80)/*enable Endpoint 0*/
#define Usb_set_EP0RST()	               (UEPRST|= 0x01)
#define Usb_clr_EP0RST()                 (UEPRST&= ~0x01)
#define Usb_set_EP1RST()	               (UEPRST|= 0x02)
#define Usb_clr_EP1RST()                 (UEPRST&= ~0x02)
#define Usb_set_EP2RST()	               (UEPRST|= 0x04)
#define Usb_clr_EP2RST()                 (UEPRST&= ~0x04)
#define Usb_set_STALLRQ_bit()             (UEPSTAX |= 0x20)
#define Usb_clear_STALLRQ_bit()           (UEPSTAX &= ~0x20)
#define Usb_stall_sent_complete()              (UEPSTAX & 0x08)
#define Usb_set_STALLRQ()               (UEPSTAX |= 0x20)