?? prev_cmp_cd.tan.qmsg
字號:
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "Mux11~97 " "Warning: Node \"Mux11~97\"" { } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 38 -1 0 } } } 0 0 "Node \"%1!s!\"" 0 0 "" 0} } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 38 -1 0 } } } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 6 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "10 " "Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "Mux2~249 " "Info: Detected gated clock \"Mux2~249\" as buffer" { } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 25 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux2~249" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux0~137 " "Info: Detected gated clock \"Mux0~137\" as buffer" { } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 25 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux0~137" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux2~250 " "Info: Detected gated clock \"Mux2~250\" as buffer" { } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 25 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux2~250" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jishu1\[1\] " "Info: Detected ripple clock \"jishu1\[1\]\" as buffer" { } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 15 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "jishu1\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jishu1\[5\] " "Info: Detected ripple clock \"jishu1\[5\]\" as buffer" { } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 15 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "jishu1\[5\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jishu1\[2\] " "Info: Detected ripple clock \"jishu1\[2\]\" as buffer" { } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 15 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "jishu1\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux2~248 " "Info: Detected gated clock \"Mux2~248\" as buffer" { } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 25 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux2~248" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jishu1\[3\] " "Info: Detected ripple clock \"jishu1\[3\]\" as buffer" { } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 15 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "jishu1\[3\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jishu1\[4\] " "Info: Detected ripple clock \"jishu1\[4\]\" as buffer" { } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 15 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "jishu1\[4\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jishu1\[0\] " "Info: Detected ripple clock \"jishu1\[0\]\" as buffer" { } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 15 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "jishu1\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register jishu1\[0\] register jishu1\[5\] 352.86 MHz 2.834 ns Internal " "Info: Clock \"clk\" has Internal fmax of 352.86 MHz between source register \"jishu1\[0\]\" and destination register \"jishu1\[5\]\" (period= 2.834 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.632 ns + Longest register register " "Info: + Longest register to register delay is 2.632 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jishu1\[0\] 1 REG LC_X12_Y4_N0 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y4_N0; Fanout = 7; REG Node = 'jishu1\[0\]'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { jishu1[0] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.395 ns) + CELL(0.340 ns) 0.735 ns Mux0~137 2 COMB LC_X12_Y4_N9 2 " "Info: 2: + IC(0.395 ns) + CELL(0.340 ns) = 0.735 ns; Loc. = LC_X12_Y4_N9; Fanout = 2; COMB Node = 'Mux0~137'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.735 ns" { jishu1[0] Mux0~137 } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.586 ns) + CELL(0.088 ns) 1.409 ns Mux2~248 3 COMB LC_X11_Y4_N9 3 " "Info: 3: + IC(0.586 ns) + CELL(0.088 ns) = 1.409 ns; Loc. = LC_X11_Y4_N9; Fanout = 3; COMB Node = 'Mux2~248'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.674 ns" { Mux0~137 Mux2~248 } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 25 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.855 ns) + CELL(0.368 ns) 2.632 ns jishu1\[5\] 4 REG LC_X12_Y4_N7 4 " "Info: 4: + IC(0.855 ns) + CELL(0.368 ns) = 2.632 ns; Loc. = LC_X12_Y4_N7; Fanout = 4; REG Node = 'jishu1\[5\]'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.223 ns" { Mux2~248 jishu1[5] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.796 ns ( 30.24 % ) " "Info: Total cell delay = 0.796 ns ( 30.24 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.836 ns ( 69.76 % ) " "Info: Total interconnect delay = 1.836 ns ( 69.76 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.632 ns" { jishu1[0] Mux0~137 Mux2~248 jishu1[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.632 ns" { jishu1[0] {} Mux0~137 {} Mux2~248 {} jishu1[5] {} } { 0.000ns 0.395ns 0.586ns 0.855ns } { 0.000ns 0.340ns 0.088ns 0.368ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.232 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.232 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.555 ns) + CELL(0.547 ns) 2.232 ns jishu1\[5\] 2 REG LC_X12_Y4_N7 4 " "Info: 2: + IC(0.555 ns) + CELL(0.547 ns) = 2.232 ns; Loc. = LC_X12_Y4_N7; Fanout = 4; REG Node = 'jishu1\[5\]'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.102 ns" { clk jishu1[5] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 75.13 % ) " "Info: Total cell delay = 1.677 ns ( 75.13 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.555 ns ( 24.87 % ) " "Info: Total interconnect delay = 0.555 ns ( 24.87 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { clk jishu1[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { clk {} clk~out0 {} jishu1[5] {} } { 0.000ns 0.000ns 0.555ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.232 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.232 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.555 ns) + CELL(0.547 ns) 2.232 ns jishu1\[0\] 2 REG LC_X12_Y4_N0 7 " "Info: 2: + IC(0.555 ns) + CELL(0.547 ns) = 2.232 ns; Loc. = LC_X12_Y4_N0; Fanout = 7; REG Node = 'jishu1\[0\]'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.102 ns" { clk jishu1[0] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 15 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 75.13 % ) " "Info: Total cell delay = 1.677 ns ( 75.13 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.555 ns ( 24.87 % ) " "Info: Total interconnect delay = 0.555 ns ( 24.87 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { clk jishu1[0] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { clk {} clk~out0 {} jishu1[0] {} } { 0.000ns 0.000ns 0.555ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { clk jishu1[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { clk {} clk~out0 {} jishu1[5] {} } { 0.000ns 0.000ns 0.555ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { clk jishu1[0] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { clk {} clk~out0 {} jishu1[0] {} } { 0.000ns 0.000ns 0.555ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 15 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" { } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 15 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.632 ns" { jishu1[0] Mux0~137 Mux2~248 jishu1[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.632 ns" { jishu1[0] {} Mux0~137 {} Mux2~248 {} jishu1[5] {} } { 0.000ns 0.395ns 0.586ns 0.855ns } { 0.000ns 0.340ns 0.088ns 0.368ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { clk jishu1[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { clk {} clk~out0 {} jishu1[5] {} } { 0.000ns 0.000ns 0.555ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { clk jishu1[0] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { clk {} clk~out0 {} jishu1[0] {} } { 0.000ns 0.000ns 0.555ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 9 " "Warning: Circuit may not operate. Detected 9 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
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