{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "jishu1\[1\] jishu2\[0\] clk 4.971 ns " "Info: Found hold time violation between source  pin or register \"jishu1\[1\]\" and destination pin or register \"jishu2\[0\]\" for clock \"clk\" (Hold time is 4.971 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.349 ns + Largest " "Info: + Largest clock skew is 6.349 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.581 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.581 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.555 ns) + CELL(0.720 ns) 2.405 ns jishu1\[3\] 2 REG LC_X12_Y4_N8 6 " "Info: 2: + IC(0.555 ns) + CELL(0.720 ns) = 2.405 ns; Loc. = LC_X12_Y4_N8; Fanout = 6; REG Node = 'jishu1\[3\]'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.275 ns" { clk jishu1[3] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.907 ns) + CELL(0.454 ns) 3.766 ns Mux2~250 3 COMB LC_X11_Y4_N3 1 " "Info: 3: + IC(0.907 ns) + CELL(0.454 ns) = 3.766 ns; Loc. = LC_X11_Y4_N3; Fanout = 1; COMB Node = 'Mux2~250'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.361 ns" { jishu1[3] Mux2~250 } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.309 ns) + CELL(0.340 ns) 4.415 ns Mux2~251 4 COMB LC_X11_Y4_N4 3 " "Info: 4: + IC(0.309 ns) + CELL(0.340 ns) = 4.415 ns; Loc. = LC_X11_Y4_N4; Fanout = 3; COMB Node = 'Mux2~251'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.649 ns" { Mux2~250 Mux2~251 } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.078 ns) + CELL(0.088 ns) 8.581 ns jishu2\[0\] 5 REG LC_X11_Y4_N6 4 " "Info: 5: + IC(4.078 ns) + CELL(0.088 ns) = 8.581 ns; Loc. = LC_X11_Y4_N6; Fanout = 4; REG Node = 'jishu2\[0\]'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "4.166 ns" { Mux2~251 jishu2[0] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.732 ns ( 31.84 % ) " "Info: Total cell delay = 2.732 ns ( 31.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.849 ns ( 68.16 % ) " "Info: Total interconnect delay = 5.849 ns ( 68.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.581 ns" { clk jishu1[3] Mux2~250 Mux2~251 jishu2[0] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "8.581 ns" { clk {} clk~out0 {} jishu1[3] {} Mux2~250 {} Mux2~251 {} jishu2[0] {} } { 0.000ns 0.000ns 0.555ns 0.907ns 0.309ns 4.078ns } { 0.000ns 1.130ns 0.720ns 0.454ns 0.340ns 0.088ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.232 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.232 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.555 ns) + CELL(0.547 ns) 2.232 ns jishu1\[1\] 2 REG LC_X12_Y4_N9 5 " "Info: 2: + IC(0.555 ns) + CELL(0.547 ns) = 2.232 ns; Loc. = LC_X12_Y4_N9; Fanout = 5; REG Node = 'jishu1\[1\]'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.102 ns" { clk jishu1[1] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 75.13 % ) " "Info: Total cell delay = 1.677 ns ( 75.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.555 ns ( 24.87 % ) " "Info: Total interconnect delay = 0.555 ns ( 24.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { clk jishu1[1] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { clk {} clk~out0 {} jishu1[1] {} } { 0.000ns 0.000ns 0.555ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.581 ns" { clk jishu1[3] Mux2~250 Mux2~251 jishu2[0] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "8.581 ns" { clk {} clk~out0 {} jishu1[3] {} Mux2~250 {} Mux2~251 {} jishu2[0] {} } { 0.000ns 0.000ns 0.555ns 0.907ns 0.309ns 4.078ns } { 0.000ns 1.130ns 0.720ns 0.454ns 0.340ns 0.088ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { clk jishu1[1] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { clk {} clk~out0 {} jishu1[1] {} } { 0.000ns 0.000ns 0.555ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns - " "Info: - Micro clock to output delay of source is 0.173 ns" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 15 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.205 ns - Shortest register register " "Info: - Shortest register to register delay is 1.205 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jishu1\[1\] 1 REG LC_X12_Y4_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X12_Y4_N9; Fanout = 5; REG Node = 'jishu1\[1\]'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { jishu1[1] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.291 ns) 0.291 ns Mux0~137 2 COMB LC_X12_Y4_N9 2 " "Info: 2: + IC(0.000 ns) + CELL(0.291 ns) = 0.291 ns; Loc. = LC_X12_Y4_N9; Fanout = 2; COMB Node = 'Mux0~137'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.291 ns" { jishu1[1] Mux0~137 } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.574 ns) + CELL(0.340 ns) 1.205 ns jishu2\[0\] 3 REG LC_X11_Y4_N6 4 " "Info: 3: + IC(0.574 ns) + CELL(0.340 ns) = 1.205 ns; Loc. = LC_X11_Y4_N6; Fanout = 4; REG Node = 'jishu2\[0\]'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.914 ns" { Mux0~137 jishu2[0] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.631 ns ( 52.37 % ) " "Info: Total cell delay = 0.631 ns ( 52.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.574 ns ( 47.63 % ) " "Info: Total interconnect delay = 0.574 ns ( 47.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.205 ns" { jishu1[1] Mux0~137 jishu2[0] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "1.205 ns" { jishu1[1] {} Mux0~137 {} jishu2[0] {} } { 0.000ns 0.000ns 0.574ns } { 0.000ns 0.291ns 0.340ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 15 -1 0 } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 23 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.581 ns" { clk jishu1[3] Mux2~250 Mux2~251 jishu2[0] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "8.581 ns" { clk {} clk~out0 {} jishu1[3] {} Mux2~250 {} Mux2~251 {} jishu2[0] {} } { 0.000ns 0.000ns 0.555ns 0.907ns 0.309ns 4.078ns } { 0.000ns 1.130ns 0.720ns 0.454ns 0.340ns 0.088ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.232 ns" { clk jishu1[1] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.232 ns" { clk {} clk~out0 {} jishu1[1] {} } { 0.000ns 0.000ns 0.555ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.205 ns" { jishu1[1] Mux0~137 jishu2[0] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "1.205 ns" { jishu1[1] {} Mux0~137 {} jishu2[0] {} } { 0.000ns 0.000ns 0.574ns } { 0.000ns 0.291ns 0.340ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[0\] jishu2\[2\] 13.294 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\[0\]\" through register \"jishu2\[2\]\" is 13.294 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.580 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.580 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.555 ns) + CELL(0.720 ns) 2.405 ns jishu1\[3\] 2 REG LC_X12_Y4_N8 6 " "Info: 2: + IC(0.555 ns) + CELL(0.720 ns) = 2.405 ns; Loc. = LC_X12_Y4_N8; Fanout = 6; REG Node = 'jishu1\[3\]'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.275 ns" { clk jishu1[3] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.907 ns) + CELL(0.454 ns) 3.766 ns Mux2~250 3 COMB LC_X11_Y4_N3 1 " "Info: 3: + IC(0.907 ns) + CELL(0.454 ns) = 3.766 ns; Loc. = LC_X11_Y4_N3; Fanout = 1; COMB Node = 'Mux2~250'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.361 ns" { jishu1[3] Mux2~250 } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.309 ns) + CELL(0.340 ns) 4.415 ns Mux2~251 4 COMB LC_X11_Y4_N4 3 " "Info: 4: + IC(0.309 ns) + CELL(0.340 ns) = 4.415 ns; Loc. = LC_X11_Y4_N4; Fanout = 3; COMB Node = 'Mux2~251'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.649 ns" { Mux2~250 Mux2~251 } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 25 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.077 ns) + CELL(0.088 ns) 8.580 ns jishu2\[2\] 5 REG LC_X11_Y4_N8 4 " "Info: 5: + IC(4.077 ns) + CELL(0.088 ns) = 8.580 ns; Loc. = LC_X11_Y4_N8; Fanout = 4; REG Node = 'jishu2\[2\]'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "4.165 ns" { Mux2~251 jishu2[2] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.732 ns ( 31.84 % ) " "Info: Total cell delay = 2.732 ns ( 31.84 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.848 ns ( 68.16 % ) " "Info: Total interconnect delay = 5.848 ns ( 68.16 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.580 ns" { clk jishu1[3] Mux2~250 Mux2~251 jishu2[2] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "8.580 ns" { clk {} clk~out0 {} jishu1[3] {} Mux2~250 {} Mux2~251 {} jishu2[2] {} } { 0.000ns 0.000ns 0.555ns 0.907ns 0.309ns 4.077ns } { 0.000ns 1.130ns 0.720ns 0.454ns 0.340ns 0.088ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.714 ns + Longest register pin " "Info: + Longest register to pin delay is 4.714 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jishu2\[2\] 1 REG LC_X11_Y4_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X11_Y4_N8; Fanout = 4; REG Node = 'jishu2\[2\]'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { jishu2[2] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.318 ns) 1.318 ns Mux11~97 2 COMB LOOP LC_X11_Y4_N1 2 " "Info: 2: + IC(0.000 ns) + CELL(1.318 ns) = 1.318 ns; Loc. = LC_X11_Y4_N1; Fanout = 2; COMB LOOP Node = 'Mux11~97'" { { "Info" "ITDB_PART_OF_SCC" "Mux11~97 LC_X11_Y4_N1 " "Info: Loc. = LC_X11_Y4_N1; Node \"Mux11~97\"" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Mux11~97 } "NODE_NAME" } }  } 0 0 "Loc. = %2!s!; Node \"%1!s!\"" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { Mux11~97 } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 38 -1 0 } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.318 ns" { jishu2[2] Mux11~97 } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.774 ns) + CELL(1.622 ns) 4.714 ns dout\[0\] 3 PIN PIN_73 0 " "Info: 3: + IC(1.774 ns) + CELL(1.622 ns) = 4.714 ns; Loc. = PIN_73; Fanout = 0; PIN Node = 'dout\[0\]'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.396 ns" { Mux11~97 dout[0] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.940 ns ( 62.37 % ) " "Info: Total cell delay = 2.940 ns ( 62.37 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.774 ns ( 37.63 % ) " "Info: Total interconnect delay = 1.774 ns ( 37.63 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "4.714 ns" { jishu2[2] Mux11~97 dout[0] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "4.714 ns" { jishu2[2] {} Mux11~97 {} dout[0] {} } { 0.000ns 0.000ns 1.774ns } { 0.000ns 1.318ns 1.622ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.580 ns" { clk jishu1[3] Mux2~250 Mux2~251 jishu2[2] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "8.580 ns" { clk {} clk~out0 {} jishu1[3] {} Mux2~250 {} Mux2~251 {} jishu2[2] {} } { 0.000ns 0.000ns 0.555ns 0.907ns 0.309ns 4.077ns } { 0.000ns 1.130ns 0.720ns 0.454ns 0.340ns 0.088ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "4.714 ns" { jishu2[2] Mux11~97 dout[0] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "4.714 ns" { jishu2[2] {} Mux11~97 {} dout[0] {} } { 0.000ns 0.000ns 1.774ns } { 0.000ns 1.318ns 1.622ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 11 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Nov 03 22:21:55 2008 " "Info: Processing ended: Mon Nov 03 22:21:55 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}