{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 6 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "10 " "Warning: Found 10 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "jishu2\[2\] " "Info: Detected ripple clock \"jishu2\[2\]\" as buffer" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 24 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "jishu2\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jishu2\[1\] " "Info: Detected ripple clock \"jishu2\[1\]\" as buffer" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 24 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "jishu2\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jishu2\[0\] " "Info: Detected ripple clock \"jishu2\[0\]\" as buffer" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 24 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "jishu2\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux8~230 " "Info: Detected gated clock \"Mux8~230\" as buffer" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 37 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux8~230" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux8~229 " "Info: Detected gated clock \"Mux8~229\" as buffer" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 37 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux8~229" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux8~228 " "Info: Detected gated clock \"Mux8~228\" as buffer" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 37 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux8~228" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "dout_tmp\[2\]~1564 " "Info: Detected gated clock \"dout_tmp\[2\]~1564\" as buffer" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "dout_tmp\[2\]~1564" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jishu1\[4\] " "Info: Detected ripple clock \"jishu1\[4\]\" as buffer" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 16 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "jishu1\[4\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jishu1\[3\] " "Info: Detected ripple clock \"jishu1\[3\]\" as buffer" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 16 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "jishu1\[3\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "jishu1\[5\] " "Info: Detected ripple clock \"jishu1\[5\]\" as buffer" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 16 -1 0 } } { "d:/quartusii/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/quartusii/quartus/bin/Assignment Editor.qase" 1 { { 0 "jishu1\[5\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register jishu1\[2\] register jishu1\[5\] 298.86 MHz 3.346 ns Internal " "Info: Clock \"clk\" has Internal fmax of 298.86 MHz between source register \"jishu1\[2\]\" and destination register \"jishu1\[5\]\" (period= 3.346 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.144 ns + Longest register register " "Info: + Longest register to register delay is 3.144 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jishu1\[2\] 1 REG LC_X9_Y16_N7 28 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y16_N7; Fanout = 28; REG Node = 'jishu1\[2\]'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { jishu1[2] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.288 ns) + CELL(0.454 ns) 1.742 ns Equal0~666 2 COMB LC_X8_Y17_N1 2 " "Info: 2: + IC(1.288 ns) + CELL(0.454 ns) = 1.742 ns; Loc. = LC_X8_Y17_N1; Fanout = 2; COMB Node = 'Equal0~666'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.742 ns" { jishu1[2] Equal0~666 } "NODE_NAME" } } { "d:/quartusii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/quartusii/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.935 ns) + CELL(0.467 ns) 3.144 ns jishu1\[5\] 3 REG LC_X9_Y16_N8 28 " "Info: 3: + IC(0.935 ns) + CELL(0.467 ns) = 3.144 ns; Loc. = LC_X9_Y16_N8; Fanout = 28; REG Node = 'jishu1\[5\]'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.402 ns" { Equal0~666 jishu1[5] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.921 ns ( 29.29 % ) " "Info: Total cell delay = 0.921 ns ( 29.29 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.223 ns ( 70.71 % ) " "Info: Total interconnect delay = 2.223 ns ( 70.71 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.144 ns" { jishu1[2] Equal0~666 jishu1[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "3.144 ns" { jishu1[2] {} Equal0~666 {} jishu1[5] {} } { 0.000ns 1.288ns 0.935ns } { 0.000ns 0.454ns 0.467ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.272 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.595 ns) + CELL(0.547 ns) 2.272 ns jishu1\[5\] 2 REG LC_X9_Y16_N8 28 " "Info: 2: + IC(0.595 ns) + CELL(0.547 ns) = 2.272 ns; Loc. = LC_X9_Y16_N8; Fanout = 28; REG Node = 'jishu1\[5\]'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.142 ns" { clk jishu1[5] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 73.81 % ) " "Info: Total cell delay = 1.677 ns ( 73.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.595 ns ( 26.19 % ) " "Info: Total interconnect delay = 0.595 ns ( 26.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.272 ns" { clk jishu1[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.272 ns" { clk {} clk~out0 {} jishu1[5] {} } { 0.000ns 0.000ns 0.595ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.272 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.595 ns) + CELL(0.547 ns) 2.272 ns jishu1\[2\] 2 REG LC_X9_Y16_N7 28 " "Info: 2: + IC(0.595 ns) + CELL(0.547 ns) = 2.272 ns; Loc. = LC_X9_Y16_N7; Fanout = 28; REG Node = 'jishu1\[2\]'" {  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.142 ns" { clk jishu1[2] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 73.81 % ) " "Info: Total cell delay = 1.677 ns ( 73.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.595 ns ( 26.19 % ) " "Info: Total interconnect delay = 0.595 ns ( 26.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.272 ns" { clk jishu1[2] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.272 ns" { clk {} clk~out0 {} jishu1[2] {} } { 0.000ns 0.000ns 0.595ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.272 ns" { clk jishu1[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.272 ns" { clk {} clk~out0 {} jishu1[5] {} } { 0.000ns 0.000ns 0.595ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.272 ns" { clk jishu1[2] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.272 ns" { clk {} clk~out0 {} jishu1[2] {} } { 0.000ns 0.000ns 0.595ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" {  } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 16 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.144 ns" { jishu1[2] Equal0~666 jishu1[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "3.144 ns" { jishu1[2] {} Equal0~666 {} jishu1[5] {} } { 0.000ns 1.288ns 0.935ns } { 0.000ns 0.454ns 0.467ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.272 ns" { clk jishu1[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.272 ns" { clk {} clk~out0 {} jishu1[5] {} } { 0.000ns 0.000ns 0.595ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.272 ns" { clk jishu1[2] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.272 ns" { clk {} clk~out0 {} jishu1[2] {} } { 0.000ns 0.000ns 0.595ns } { 0.000ns 1.130ns 0.547ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 48 " "Warning: Circuit may not operate. Detected 48 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}