?? cd.tan.qmsg
字號:
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "jishu1\[1\] dout_tmp\[5\] clk 4.27 ns " "Info: Found hold time violation between source pin or register \"jishu1\[1\]\" and destination pin or register \"dout_tmp\[5\]\" for clock \"clk\" (Hold time is 4.27 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "6.205 ns + Largest " "Info: + Largest clock skew is 6.205 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 8.477 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 8.477 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.595 ns) + CELL(0.720 ns) 2.445 ns jishu1\[5\] 2 REG LC_X9_Y16_N8 28 " "Info: 2: + IC(0.595 ns) + CELL(0.720 ns) = 2.445 ns; Loc. = LC_X9_Y16_N8; Fanout = 28; REG Node = 'jishu1\[5\]'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.315 ns" { clk jishu1[5] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.015 ns) + CELL(0.340 ns) 3.800 ns dout_tmp\[2\]~1564 3 COMB LC_X8_Y14_N9 3 " "Info: 3: + IC(1.015 ns) + CELL(0.340 ns) = 3.800 ns; Loc. = LC_X8_Y14_N9; Fanout = 3; COMB Node = 'dout_tmp\[2\]~1564'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.355 ns" { jishu1[5] dout_tmp[2]~1564 } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.340 ns) 4.698 ns Mux8~230 4 COMB LC_X7_Y14_N4 8 " "Info: 4: + IC(0.558 ns) + CELL(0.340 ns) = 4.698 ns; Loc. = LC_X7_Y14_N4; Fanout = 8; COMB Node = 'Mux8~230'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.898 ns" { dout_tmp[2]~1564 Mux8~230 } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.554 ns) + CELL(0.225 ns) 8.477 ns dout_tmp\[5\] 5 REG LC_X9_Y16_N3 1 " "Info: 5: + IC(3.554 ns) + CELL(0.225 ns) = 8.477 ns; Loc. = LC_X9_Y16_N3; Fanout = 1; REG Node = 'dout_tmp\[5\]'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.779 ns" { Mux8~230 dout_tmp[5] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.755 ns ( 32.50 % ) " "Info: Total cell delay = 2.755 ns ( 32.50 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.722 ns ( 67.50 % ) " "Info: Total interconnect delay = 5.722 ns ( 67.50 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.477 ns" { clk jishu1[5] dout_tmp[2]~1564 Mux8~230 dout_tmp[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "8.477 ns" { clk {} clk~out0 {} jishu1[5] {} dout_tmp[2]~1564 {} Mux8~230 {} dout_tmp[5] {} } { 0.000ns 0.000ns 0.595ns 1.015ns 0.558ns 3.554ns } { 0.000ns 1.130ns 0.720ns 0.340ns 0.340ns 0.225ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.272 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 2.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.595 ns) + CELL(0.547 ns) 2.272 ns jishu1\[1\] 2 REG LC_X9_Y16_N9 39 " "Info: 2: + IC(0.595 ns) + CELL(0.547 ns) = 2.272 ns; Loc. = LC_X9_Y16_N9; Fanout = 39; REG Node = 'jishu1\[1\]'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.142 ns" { clk jishu1[1] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 73.81 % ) " "Info: Total cell delay = 1.677 ns ( 73.81 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.595 ns ( 26.19 % ) " "Info: Total interconnect delay = 0.595 ns ( 26.19 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.272 ns" { clk jishu1[1] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.272 ns" { clk {} clk~out0 {} jishu1[1] {} } { 0.000ns 0.000ns 0.595ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.477 ns" { clk jishu1[5] dout_tmp[2]~1564 Mux8~230 dout_tmp[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "8.477 ns" { clk {} clk~out0 {} jishu1[5] {} dout_tmp[2]~1564 {} Mux8~230 {} dout_tmp[5] {} } { 0.000ns 0.000ns 0.595ns 1.015ns 0.558ns 3.554ns } { 0.000ns 1.130ns 0.720ns 0.340ns 0.340ns 0.225ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.272 ns" { clk jishu1[1] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.272 ns" { clk {} clk~out0 {} jishu1[1] {} } { 0.000ns 0.000ns 0.595ns } { 0.000ns 1.130ns 0.547ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns - " "Info: - Micro clock to output delay of source is 0.173 ns" { } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 16 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.762 ns - Shortest register register " "Info: - Shortest register to register delay is 1.762 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns jishu1\[1\] 1 REG LC_X9_Y16_N9 39 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y16_N9; Fanout = 39; REG Node = 'jishu1\[1\]'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { jishu1[1] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.437 ns) + CELL(0.225 ns) 0.662 ns dout_tmp\[5\]~1576 2 COMB LC_X9_Y16_N6 1 " "Info: 2: + IC(0.437 ns) + CELL(0.225 ns) = 0.662 ns; Loc. = LC_X9_Y16_N6; Fanout = 1; COMB Node = 'dout_tmp\[5\]~1576'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.662 ns" { jishu1[1] dout_tmp[5]~1576 } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.328 ns) + CELL(0.088 ns) 1.078 ns Mux2~220 3 COMB LC_X9_Y16_N0 1 " "Info: 3: + IC(0.328 ns) + CELL(0.088 ns) = 1.078 ns; Loc. = LC_X9_Y16_N0; Fanout = 1; COMB Node = 'Mux2~220'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.416 ns" { dout_tmp[5]~1576 Mux2~220 } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.088 ns) 1.306 ns Mux2~221 4 COMB LC_X9_Y16_N1 1 " "Info: 4: + IC(0.140 ns) + CELL(0.088 ns) = 1.306 ns; Loc. = LC_X9_Y16_N1; Fanout = 1; COMB Node = 'Mux2~221'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.228 ns" { Mux2~220 Mux2~221 } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.088 ns) 1.534 ns Mux2~223 5 COMB LC_X9_Y16_N2 1 " "Info: 5: + IC(0.140 ns) + CELL(0.088 ns) = 1.534 ns; Loc. = LC_X9_Y16_N2; Fanout = 1; COMB Node = 'Mux2~223'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.228 ns" { Mux2~221 Mux2~223 } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.140 ns) + CELL(0.088 ns) 1.762 ns dout_tmp\[5\] 6 REG LC_X9_Y16_N3 1 " "Info: 6: + IC(0.140 ns) + CELL(0.088 ns) = 1.762 ns; Loc. = LC_X9_Y16_N3; Fanout = 1; REG Node = 'dout_tmp\[5\]'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.228 ns" { Mux2~223 dout_tmp[5] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.577 ns ( 32.75 % ) " "Info: Total cell delay = 0.577 ns ( 32.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.185 ns ( 67.25 % ) " "Info: Total interconnect delay = 1.185 ns ( 67.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.762 ns" { jishu1[1] dout_tmp[5]~1576 Mux2~220 Mux2~221 Mux2~223 dout_tmp[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "1.762 ns" { jishu1[1] {} dout_tmp[5]~1576 {} Mux2~220 {} Mux2~221 {} Mux2~223 {} dout_tmp[5] {} } { 0.000ns 0.437ns 0.328ns 0.140ns 0.140ns 0.140ns } { 0.000ns 0.225ns 0.088ns 0.088ns 0.088ns 0.088ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" { } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" { } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 16 -1 0 } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0} } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.477 ns" { clk jishu1[5] dout_tmp[2]~1564 Mux8~230 dout_tmp[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "8.477 ns" { clk {} clk~out0 {} jishu1[5] {} dout_tmp[2]~1564 {} Mux8~230 {} dout_tmp[5] {} } { 0.000ns 0.000ns 0.595ns 1.015ns 0.558ns 3.554ns } { 0.000ns 1.130ns 0.720ns 0.340ns 0.340ns 0.225ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "2.272 ns" { clk jishu1[1] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "2.272 ns" { clk {} clk~out0 {} jishu1[1] {} } { 0.000ns 0.000ns 0.595ns } { 0.000ns 1.130ns 0.547ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.762 ns" { jishu1[1] dout_tmp[5]~1576 Mux2~220 Mux2~221 Mux2~223 dout_tmp[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "1.762 ns" { jishu1[1] {} dout_tmp[5]~1576 {} Mux2~220 {} Mux2~221 {} Mux2~223 {} dout_tmp[5] {} } { 0.000ns 0.437ns 0.328ns 0.140ns 0.140ns 0.140ns } { 0.000ns 0.225ns 0.088ns 0.088ns 0.088ns 0.088ns } "" } } } 0 0 "Found hold time violation between source pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dout\[5\] dout_tmp\[5\] 11.692 ns register " "Info: tco from clock \"clk\" to destination pin \"dout\[5\]\" through register \"dout_tmp\[5\]\" is 11.692 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 8.477 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 8.477 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns clk 1 CLK PIN_29 6 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_29; Fanout = 6; CLK Node = 'clk'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 6 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.595 ns) + CELL(0.720 ns) 2.445 ns jishu1\[5\] 2 REG LC_X9_Y16_N8 28 " "Info: 2: + IC(0.595 ns) + CELL(0.720 ns) = 2.445 ns; Loc. = LC_X9_Y16_N8; Fanout = 28; REG Node = 'jishu1\[5\]'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.315 ns" { clk jishu1[5] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 16 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.015 ns) + CELL(0.340 ns) 3.800 ns dout_tmp\[2\]~1564 3 COMB LC_X8_Y14_N9 3 " "Info: 3: + IC(1.015 ns) + CELL(0.340 ns) = 3.800 ns; Loc. = LC_X8_Y14_N9; Fanout = 3; COMB Node = 'dout_tmp\[2\]~1564'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "1.355 ns" { jishu1[5] dout_tmp[2]~1564 } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.558 ns) + CELL(0.340 ns) 4.698 ns Mux8~230 4 COMB LC_X7_Y14_N4 8 " "Info: 4: + IC(0.558 ns) + CELL(0.340 ns) = 4.698 ns; Loc. = LC_X7_Y14_N4; Fanout = 8; COMB Node = 'Mux8~230'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "0.898 ns" { dout_tmp[2]~1564 Mux8~230 } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 37 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.554 ns) + CELL(0.225 ns) 8.477 ns dout_tmp\[5\] 5 REG LC_X9_Y16_N3 1 " "Info: 5: + IC(3.554 ns) + CELL(0.225 ns) = 8.477 ns; Loc. = LC_X9_Y16_N3; Fanout = 1; REG Node = 'dout_tmp\[5\]'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.779 ns" { Mux8~230 dout_tmp[5] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.755 ns ( 32.50 % ) " "Info: Total cell delay = 2.755 ns ( 32.50 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.722 ns ( 67.50 % ) " "Info: Total interconnect delay = 5.722 ns ( 67.50 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.477 ns" { clk jishu1[5] dout_tmp[2]~1564 Mux8~230 dout_tmp[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "8.477 ns" { clk {} clk~out0 {} jishu1[5] {} dout_tmp[2]~1564 {} Mux8~230 {} dout_tmp[5] {} } { 0.000ns 0.000ns 0.595ns 1.015ns 0.558ns 3.554ns } { 0.000ns 1.130ns 0.720ns 0.340ns 0.340ns 0.225ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" { } { { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.215 ns + Longest register pin " "Info: + Longest register to pin delay is 3.215 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dout_tmp\[5\] 1 REG LC_X9_Y16_N3 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y16_N3; Fanout = 1; REG Node = 'dout_tmp\[5\]'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "" { dout_tmp[5] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.593 ns) + CELL(1.622 ns) 3.215 ns dout\[5\] 2 PIN PIN_226 0 " "Info: 2: + IC(1.593 ns) + CELL(1.622 ns) = 3.215 ns; Loc. = PIN_226; Fanout = 0; PIN Node = 'dout\[5\]'" { } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.215 ns" { dout_tmp[5] dout[5] } "NODE_NAME" } } { "cd.vhd" "" { Text "E:/QuartueII/cd/cd.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.622 ns ( 50.45 % ) " "Info: Total cell delay = 1.622 ns ( 50.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.593 ns ( 49.55 % ) " "Info: Total interconnect delay = 1.593 ns ( 49.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.215 ns" { dout_tmp[5] dout[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "3.215 ns" { dout_tmp[5] {} dout[5] {} } { 0.000ns 1.593ns } { 0.000ns 1.622ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} } { { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "8.477 ns" { clk jishu1[5] dout_tmp[2]~1564 Mux8~230 dout_tmp[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "8.477 ns" { clk {} clk~out0 {} jishu1[5] {} dout_tmp[2]~1564 {} Mux8~230 {} dout_tmp[5] {} } { 0.000ns 0.000ns 0.595ns 1.015ns 0.558ns 3.554ns } { 0.000ns 1.130ns 0.720ns 0.340ns 0.340ns 0.225ns } "" } } { "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/quartusii/quartus/bin/TimingClosureFloorplan.fld" "" "3.215 ns" { dout_tmp[5] dout[5] } "NODE_NAME" } } { "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/quartusii/quartus/bin/Technology_Viewer.qrui" "3.215 ns" { dout_tmp[5] {} dout[5] {} } { 0.000ns 1.593ns } { 0.000ns 1.622ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 15 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 15 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "115 " "Info: Allocated 115 megabytes of memory during processing" { } { } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 04 20:11:35 2008 " "Info: Processing ended: Tue Nov 04 20:11:35 2008" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
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