/* *  head.S * *  Copyright (C) 2001-2002 Hayden Luo * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. * *  32-bit startup code for s3c5410b board */#include "config.h"#include "board.h"	.globl stext	.globl system_table_offset	.globl _rom_base.section ".text"stext:	b	__init_entrysystem_table_offset:	.long	SYSTEM_TABLE_OFFSET_rom_base:	.long   stext__init_entry:	ldr	pc, =__entry__entry:/* * Setup Register SYSCFG *    - Special Register Base Addr : 0x3ff0000 *    - Cache and Write Buffer Enable according to the environments *    - Check DRAM type : Normal / SDRAM */	ldr	r0, =SYSCFG	ldr	r1, =0x87FFFF80         /* Start_addr = 0x3FF00000 */	str	r1, [r0]                /* Cache OFF, Write Buffer OFF, 4K SRAM, 4K CACHE *//* * SysInitVars: Initialise the DATA and BSS sections. * * The DATA section is initialised by copying data from the end of the * ROM image (given by _etext) to the start of the RAM image * (given by __data_start), stopping when we reach _edata. * All data from _edata to _end is then cleared to 0 *//* * Load up the linker defined values for the static data copy */	ldr	r0, =_etext	ldr	r1, =__data_start	ldr	r3, =_edata/* * But first check whether we are trying to copy to the same address. * If so, this means that the image was linked as an application image * with the DATA section immediately following the CODE section. * Therefore there is nothing to copy since the data is already in place */	cmp	r0, r1	beq	1f/* * Stop on CS (ie R1 becomes >= R3). */0:	cmp	r1, r3	ldrcc	r2, [r0], #4	strcc	r2, [r1], #4	bcc	0b/* * Clear remainder of data to _end to 0 */1:	ldr	r1, =_end	mov	r2, #02:	cmp	r3, r1	strcc	r2, [r3], #4	bcc	2b/* * Now set up the BSPs SVC stack */	mrs	r0, cpsr	bic	r0, r0, #PSR_MODE_MASK	orr	r1, r0, #PSR_SVC_MODE	msr	cpsr_cf, r1	ldr	sp, =__stack/* * Cache Flush & Enable if requested */	ldr	r0, =0x11000000         /* Cache Flush */	mov	r1, #0	mov	r2, #256                1:	str	r1, [r0], #4	subs	r2, r2, #1	bne	1b	nop	ldr	r0, =SYSCFG	ldr	r2, [r0]	orr	r2, r2, #6	str	r2, [r0]                /* Cache, Write Buffer Enable */bios_start:	bl	bios_main	mov	r3, r0	ldr	r0, =SYSCFG	ldr	r1, =0x87FFFF90         /* Start_addr = 0x3FF00000 */	str	r1, [r0]                /* Cache OFF, Write Buffer OFF, 0K SRAM, 8K CACHE *//* * Cache Flush & Enable if requested */	ldr	r0, =0x11000000         /* Cache Flush */	mov	r1, #0	mov	r2, #256                1:	str	r1, [r0], #4	subs	r2, r2, #1	bne	1b	nop	ldr	r0, =SYSCFG	ldr	r2, [r0]	orr	r2, r2, #6	str	r2, [r0]                /* Cache, Write Buffer Enable *//* * Call sys_init, it should never return. */sys_start:	mov	pc, r3/* * Define stack for supervisor modes */	.align	.section ".bss"