?? usbotg.h
字號:
#ifndef _USB_OTG_H_
#define _USB_OTG_H_
#define AHB_MODE
//#define AHB_AUTO_DMA
#define NUM_ETDS 8
#define NUM_EPS 4
#define CTL_TYPE 0
#define ISO_TYPE 1
#define BLK_TYPE 2
#define INT_TYPE 3
#define IN_TYPE 2
#define OUT_TYPE 1
#define SETUP_TYPE 0
#define RSVD_TYPE 3
#define RE_DATA0 0x3
#define RE_DATA1 0xb
#define RH_NONE_SET 0x00000000
#define RH_ALL_SET 0xffffffff
#define RH_PORT_CONNECTED 0x00000001
#define RH_PORT_ENABLED 0x00000002
#define RH_PORT_CLR_ENABLED 0x00000001
#define RH_PORT_SUSPENDED 0x00000004
#define RH_PORT_RESUME 0x00000008
#define RH_PORT_OVERCURRENT 0x00000008
#define RH_PORT_RESETTING 0x00000010
#define RH_PORT_POWERED 0x00000100
#define RH_PORT_CLR_POWER 0x00000200
#define RH_PORT_LOWSPEED 0x00000200
#define RH_PORT_C_CONNECT 0x00010000
#define RH_PORT_C_ENABLE 0x00020000
#define RH_PORT_C_SUSPEND 0x00040000
#define RH_PORT_C_OVERCURRENT 0x00080000
#define RH_PORT_C_RESET 0x00100000
#define RH_STAT_SET_CONNECT_WUP 0x00008000
#define RH_STAT_CLR_CONNECT_WUP 0x80000000
#define TL_NONE_SET 0x00000000
#define TL_ALL_SET 0xffffffff
#define TL_HW_MODE_MASK 0xfffffffC
#define TL_OTGX_MASK 0xffffff3f
#define TL_XCVR_MASK 0xffffffCf
#define TL_TEST_MASK 0xffff7fff
#define TL_HW_HNP_MODE 0x00000000
#define TL_HOST_ONLY_MODE 0x00000001
#define TL_FUNC_HOST_MODE 0x00000002
#define TL_SW_HNP_MODE 0x00000003
#define TL_TEST_MODE 0x00008000
#define TL_OTGX_TX_DIFF 0x00000000
#define TL_OTGX_RX_DIFF 0x00000000
#define TL_OTGX_TX_SINGLE 0x00000080
#define TL_OTGX_RX_SINGLE 0x00000040
#define TL_XCVR_TX_DIFF 0x00000000
#define TL_XCVR_RX_DIFF 0x00000000
#define TL_XCVR_TX_SINGLE 0x00000020
#define TL_XCVR_RX_SINGLE 0x00000010
#define XCVR_TX_RX_DIFF 0
#define XCVR_TX_RX_SINGLE 3
#define XCVR_TX_SINGLE_RX_DIFF 2
#define XCVR_TX_DIFF_RX_SINGLE 1
#define TL_CHIP_CLOCK_ON 0x00000001
#define TL_HOST_CLOCK_ON 0x00000002
#define TL_FUNC_CLOCK_ON 0x00000004
#define HC_USB_STATE_MASK 0x0000000c
#define HC_USB_RESET 0x00000000
#define HC_USB_RESUME 0x00000004
#define HC_USB_OPERATIONAL 0x00000008
#define HC_USB_SUSPEND 0x0000000c
#define HC_SOFT_RESET 0x80000000
#define TL_RESET_HOST_CTRL 0x00000001
#define TL_RESET_HOST_HSIE 0x00000002
#define TL_RESET_HOST_HRH 0x00000004
#define TL_RESET_FUNC_FSIE 0x00000008
#define TL_RESET_FUNC_CTRL 0x00000010
#define TL_RESET_CTRL_CTRL 0x00000020
/////////INTERUPT SOURCES//////////
#define TL_HOST_INT 0x00000001
#define TL_FUNCTION_INT 0x00000002
#define TL_MNP_INT 0x00000004
#define TL_ASYNC_HOST_INT 0x00000008
#define TL_ASYNC_FUNC_INT 0x00000010
#define TL_ASYNC_MNP_INT 0x00000020
//HOST_SYSTEM
#define HC_SCHED_OVER_INT 0x00000001
#define HC_DONE_REG_INT 0x00000002
#define HC_SOF_INT 0x00000004
#define HC_RESUME_INT 0x00000008
#define HC_HOST_ERROR_INT 0x00000010
#define HC_FRM_NUMB_INT 0x00000020
#define HC_PORT_CHANGE_INT 0x00000040
//FUNCTION_SYSTEM
#define FC_RESET_DETECT_INT 0x00000001
#define FC_RESUME_FINISH_INT 0x00000002
#define FC_SUSPEND_DETECT_INT 0x00000004
#define FC_DONE_REG_INT 0x00000008
#define FC_SOF_INT 0x00000010
#define FC_RESET_STATE 0x00000001
#define FC_RESUME_STATE 0x00000002
#define FC_SUSPEND_STATE 0x00000004
#define FC_ACCEPT_BAD_ISO 0x00000008
#define FC_SOFT_RESET 0x00000080
//EP Descriptor DWORD0
#define EP_DESC_DW0_STALL_BIT 0x80000000
#define EP_DESC_DW0_SETUP_BIT 0x40000000
#define EP_DESC_DW0_OVERRUN_BIT 0x20000000
#define EP_DESC_DW0_AUTOISO_BIT 0x10000000
#define EP_DESC_DW0_MPS_MASK 0x03ff0000
#define EP_DESC_DW0_FORMAT_MASK 0x0000C000
#define EP_CTRL_FORMAT 0x00000000
#define EP_ISO_FORMAT 0x00004000
#define EP_BULK_FORMAT 0x00008000
#define EP_INT_FORMAT 0x0000C000
#define EP_ISO_ONE_PACKET 0
#define EP_ISO_TWO_PACKETS 1
//EP Descriptor DWORD1
#define EP_DESC_DW1_XSA_MASK 0x0000FFFF
#define EP_DESC_DW1_YSA_MASK 0xFFFF0000
//EP Descriptor DWORD3
#define EP_DESC_DW3_BUFSIZE_MASK 0xFFE00000
#define EP_DESC_DW3_XFERSIZE_MASK 0x001FFFFF
#define EP_DESC_DW3_ISO_PKTLEN0_MASK 0x000003FF
#define EP_DESC_DW3_ISO_PKTLEN1_MASK 0x03FF0000
#define EP_DESC_DW3_ISO_FRM_COUNT_MASK 0x80000000
#define EP_DESC_DW3_ISO_ONE_PACKET (EP_ISO_ONE_PACKET << 31)
#define EP_DESC_DW3_ISO_TWO_PACKETS (EP_ISO_TWO_PACKETS << 31)
//MNP interrupts see hnp_defines.vh
#define EP_OUT_DIR 0
#define EP_IN_DIR 1
#define EP_NO_STALL 0
#define EP_STALL 1
#define EP_NO_SETUP 0
#define EP_SETUP 1
#define ETD_FS_PKT 0
#define ETD_LS_PKT 1
#define ETD_NO_HALT_PKT 0
#define ETD_HALT_PKT 1
#define ETD_TOGGLE_CARRY_0 0
#define ETD_TOGGLE_CARRY_1 1
#define ETD_NO_STOP_ON_NAK 0
#define ETD_STOP_ON_NAK 1
#define ETD_NO_BUF_ROUNDING 0
#define ETD_BUF_ROUNDING 1
#define ETD_DATA_TOGGLE_TC_1 1
#define ETD_DATA_TOGGLE_TC_0 0
#define ETD_DATA_TOGGLE_NOT_TC_1 3
#define ETD_DATA_TOGGLE_NOT_TC_0 2
#define ETD_ISO_ONE_PACKET 0
#define ETD_ISO_TWO_PACKETS 1
#define ETD_FROM_TD_DIR 0
#define ETD_SETUP_DIR 0
#define ETD_OUT_DIR 1
#define ETD_IN_DIR 2
#define ETD_RSVD_DIR 3
#define ETD_AUTO_ISO 1
#define ETD_NO_AUTO_ISO 0
#define ETD_DESC_DW0_STOP_ON_NAK 0x40000000
#define ETD_DESC_DW0_TOGGLE_CARRY_0 0x00000000
#define ETD_DESC_DW0_TOGGLE_CARRY_1 0x10000000
#define ETD_DESC_DW0_TOGGLE_CARRY_MASK 0x10000000
#define ETD_DESC_DW0_HALTED_MASK 0x08000000
#define ETD_DESC_DW0_HALTED 0x08000000
#define ETD_DESC_DW0_NOT_HALTED 0x00000000
#define ETD_DESC_DW0_MPS_MASK 0x03FF0000
#define ETD_DESC_DW0_FORMAT_MASK 0x0000C000
#define ETD_DESC_DW0_SPEED_MASK 0x00002000
#define ETD_DESC_DW0_DIRECTION_MASK 0x00001800
#define ETD_DESC_DW0_ENDPOINT_MASK 0x00000780
#define ETD_DESC_DW0_ADDRESS_MASK 0x0000007F
#define ETD_CTRL_FORMAT 0x00000000
#define ETD_ISO_FORMAT 0x00001000
#define ETD_BULK_FORMAT 0x00002000
#define ETD_INT_FORMAT 0x00003000
#define ETD_FULL_SPEED 0x00001000
#define ETD_LOW_SPEED 0x00000000
#define ETD_TD_LOW_DIR (ETD_FROM_TD_DIR<< 11)
#define ETD_TD_OUT_DIR (ETD_OUT_DIR << 11)
#define ETD_TD_IN_DIR (ETD_IN_DIR << 11)
#define ETD_TD_HIGH_DIR (ETD_RSVD_DIR << 11)
#define ETD_SETUP_DIR_PID (ETD_SETUP_DIR << 16)
#define ETD_OUT_DIR_PID (ETD_OUT_DIR << 16)
#define ETD_IN_DIR_PID (ETD_IN_DIR << 16)
#define ETD_RSVD_DIR_PID (ETD_RSVD_DIR << 16)
#define ETD_DATA_TOGGLE_FROM_TC_1 (ETD_DATA_TOGGLE_TC_1 << 22)
#define ETD_DATA_TOGGLE_FROM_TC_0 (ETD_DATA_TOGGLE_TC_0 << 22)
#define ETD_DATA_TOGGLE_FROM_NOT_TC_1 (ETD_DATA_TOGGLE_NOT_TC_1<< 22)
#define ETD_DATA_TOGGLE_FROM_NOT_TC_0 (ETD_DATA_TOGGLE_NOT_TC_0<< 22)
#define ETD_AUTOISO_SET (ETD_AUTO_ISO << 27)
#define ETD_NO_AUTOISO (ETD_NO_AUTO_ISO << 27)
//ETD Descriptor DWORD1
#define ETD_DESC_DW1_XSA_MASK 0x0000FFFF
#define ETD_DESC_DW1_YSA_MASK 0xFFFF0000
//ETD Descriptor DWORD2
#define ETD_DESC_DW2_BC_RETRY_DEL 0x000000FF
#define ETD_DESC_DW2_INT_POLL_INTV_MASK 0x000000FF
#define ETD_DESC_DW2_INT_RELPOLPOS_MASK 0x0000FF00
#define ETD_DESC_DW2_BCI_DIRECTION_MASK 0x00030000
#define ETD_DESC_DW2_BCI_BUF_ROUNDING 0x00040000
#define ETD_DESC_DW2_DEL_INT 0x00380000
#define ETD_DESC_DW2_BCI_DATA_TOGGLE 0x00C00000
#define ETD_DESC_DW2_BCI_ERR_CNT_MASK 0x0F000000
#define ETD_DESC_DW2_COMPCODE_MASK 0xF0000000
#define ETD_DESC_DW2_ISO_STARTFRM_MASK 0x0000FFFF
#define ETD_DESC_DW2_ISO_AUTOISO_MASK 0x08000000
#define ETD_DESC_DW2_ISO_FRAMECNT_MASK 0x01000000
#define ETD_DESC_DW2_ISO_ONE_PACKET (ETD_ISO_ONE_PACKET <<24)
#define ETD_DESC_DW2_ISO_TWO_PACKETS (ETD_ISO_TWO_PACKETS<<24)
#define ETD_DESC_DW3_BCI_BUFSIZE_MASK 0xFFE00000
#define ETD_DESC_DW3_BCI_XFERSIZE_MASK 0x001FFFFF
#define ETD_DESC_DW3_ISO_PKT0_LEN_MASK 0x000003FF
#define ETD_DESC_DW3_ISO_COMPCODE0_MASK 0x0000F000
#define ETD_DESC_DW3_ISO_PKT1_LEN_MASK 0x03FF0000
#define ETD_DESC_DW3_ISO_COMPCODE1_MASK 0xF0000000
#define XACT_FS_PKT 0
#define XACT_LS_PKT 1
#define XACT_OUT_PKT 0
#define XACT_IN_PKT 1
#define XACT_ISO_PKT 1
#define XACT_GOOD_TOKEN 1
#define XACT_BAD_TOKEN 0
#define XACT_GOOD_PACKET 1
#define XACT_BAD_PACKET 0
#define XACT_NON_ISO_PKT 0
#define XACT_ISO_TESTS 1
#define XACT_NON_ISO_TESTS 0
#define XACT_STOP_ON_NAK 1
#define XACT_NO_STOP_ON_NAK 0
#define XACT_GOOD_ACK 0
#define XACT_BAD_ACK 1
#define XACT_NO_ACK 2
#define XACT_BAD_PID 3
#define XACT_GOOD_HAND 0
#define XACT_BAD_HAND 1
#define XACT_NO_HAND 2
#define XACT_BAD_PID 3
#define XACT_RETRY 1
#define XACT_NO_RETRY 0
#define Ack XACT_GOOD_ACK
#define BadAck XACT_BAD_ACK
#define NoAck XACT_NO_ACK
#define XACT_TOKEN_CRC_BIT_PID_GOOD 0
#define XACT_TOKEN_CRC_BIT_GOOD 1
#define XACT_TOKEN_CRC_PID_GOOD 2
#define XACT_TOKEN_CRC_GOOD 3
#define XACT_TOKEN_BIT_PID_GOOD 4
#define XACT_TOKEN_BIT_GOOD 5
#define XACT_TOKEN_PID_GOOD 6
#define XACT_TOKEN_ALL_BAD 7
#define XACT_PKT_CRC_BIT_PID_GOOD 0
#define XACT_PKT_CRC_BIT_GOOD 1
#define XACT_PKT_CRC_PID_GOOD 2
#define XACT_PKT_CRC_GOOD 3
#define XACT_PKT_BIT_PID_GOOD 4
#define XACT_PKT_BIT_GOOD 5
#define XACT_PKT_PID_GOOD 6
#define XACT_PKT_ALL_BAD 7
//dev16 defines
#define O3_DDEVWIDTH 8
#define O3_FRWIDTH 14 // frame remaining reg data width
#define O3_FIINIT 0x2edf // frame interval reg init value
#define O3_FITEST 0x0700
/* device address and endpoint number */
#define O3_DAWIDTH 7 // dev addr data width
#define O3_EPWIDTH 4 // endpoint number data width
/* packet ids */
#define O3_PID_DATA0 0xc3 // data0 pid
#define O3_PID_DATA1 0x4b // data1 pid
#define O3_PID_SETUP 0x2d // setup pid
#define O3_PID_SOF 0xa5 // sof pid
#define O3_PID_IN 0x69 // in pid
#define O3_PID_OUT 0xe1 // out pid
#define O3_PID_ACK 0xd2 // ack pid
#define O3_PID_NAK 0x5a // nak pid
#define O3_PID_STALL 0x1e // stall pid
#define O3_PID_PRE 0x3c // pre amble pid
#define O3_PID_ERR 0x00 // pid none
// DevOut States for DevTrans
#define O3_DEVOUT_IDLE 0
#define O3_DEVOUT_PID 4
#define O3_DEVOUT_DATA 6
#define O3_DEVOUT_DATA1 2
#define O3_DEVOUT_READ 10
#define O3_DEVOUT_READ1 14
#define O3_DEVOUT_LAST 12
#define O3_DEVOUT_SENT 13
#define O3_DEVOUT_ACK 9
#define O3_DEVOUT_DONE 8
//stop
#define O3_STOPTIME 10000000000 //10000ms//170180 //48990
#define O3_CLOSETIME 20000
#define O3_CWIDTH 32
#define O3_CLK_PERIOD 20.83
#define O3_MINCYCLE 77 //80
#define O3_MINDELAY 23 //20
#define O3_DELAY_PORTCHN 80
#define O3_TEST_INTP_MAX 50
#define O3_DEVWAKEUP 4
#define O3_DEVWIDTH 4
//#define O3_LONGFRAMETIME 12000*80
//#define O3_SHORTFRAMETIME 750*80
//filenames
#define O3_FILENAMELEN 8
#define O3_FILEEXTLEN 4
#define O3_FILEDIRLEN 5
#define O3_FILE_TESTBATCH "test.bat"
#define O3_FILE_TESTDIR "test/"
#define O3_FILEEXT_INST ".ist"
#define O3_FILEEXT_MEM ".mem"
#define O3_FILEEXT_BUS ".bus"
#define O3_FILEEXT_WAKE ".wak"
#define O3_FILEEXT_PORT ".ptc"
#define O3_FILEEXT_DATA ".dat"
#define O3_FILEEXT_OUT ".ors"
#define O3_FILEEXT_IN ".irs"
#define O3_FILEEXT_INTP ".isr"
#define O3_FILEEXT_ADDR ".add"
#define O3_FILEEXT_SHM ".shm"
#define O3_FILEEXT_DEV ".dev"
#define O3_FILEEXT_BMO ".bmo"
//#define O3_SHMFILE_DATABASE "Uh124Bench.shm"
//instructions
#define O3_TEST_MAX 150000 //max number of instructions
#define O3_IPADDR_BEGIN 1
/* command format */
#define O3_TMSFILE 19:16
#define O3_MODEFILE 0
#define O3_CDELAY 27:24//25:24
#define O3_CCYCLE 31:28//27:26
#define O3_CTIME 27:24
#define O3_COPER 23:20
#define O3_CPORT 9:8
#define O3_CADDR 19:8
#define O3_CDATA 7:0
#define O3_CRESET 0
#define O3_CSLPTIME 31:24
#define O3_CSLPPWR 3:0
#define O3_CMAKER 7:0
#define O3_CMWR 0
#define O3_CMRD 1
#define O3_CPWR 2
#define O3_CPRD 3
#define O3_CSLP 4
#define O3_CMAK 5
#define O3_CCSN 6
#define O3_CRTI 7
#define O3_CDUMP 0x8
#define O3_CBMO 0x9
#define O3_CCON 0xa
#define O3_COVCN 0xb
#define O3_CMRDW 0xc
#define O3_CPWRN 0xd
#define O3_CDDIR 0xe
#define O3_CEND 0xf
#define O3_CPRST 0
#define O3_CPAUX 1
#define O3_CPDAT 2
//SIE file format
#define O3_TIMEWIDTH 32 //wakeup and portchange response
#define O3_TYPEWIDTH 8 //it will not be used, the value of portchange
#define O3_DATAWIDTH 16 //it will not be used, in and data responses
#define O3_LENWIDTH 8 //it will not be used, in data response: data length
#define O3_PKTWIDTH 8 //it will not be used, in packet response
#define O3_REWIDTH 8 //in, out and setup responses
#define O3_WAKEWIDTH 32 //wakeup response: relative delay time
#define O3_PORTCHNWIDTH 40 //portchnage response: absolute time
#define O3_PORTWIDTH 8 //the values of portchange
#define O3_INDATWIDTH 4 //in data responses: length + data
//max number of responses
#define O3_TESTBATMEMLEN 100 //max length of test batch
#define O3_INREMEMLEN 100000 //max length of in response
#define O3_OUTREMEMLEN 100 //max length of out response
#define O3_DATAMEMLEN 100000 //max length of in data
#define O3_WAKEUPMEMLEN 100 //max length of wakeup
#define O3_PORTCHNMEMLEN 10000 //max length of portchange
#define O3_ADDRMEMLEN 10000 //max length of address list
//poweron/off
#define O3_MCU_POROFF 0
#define O3_MCU_PORON 1
#define O3_DEV_POROFF 0
#define O3_DEV_PORON 1
//Dev states
#define O3_DEVSTATEWIDTH 3
#define O3_DEV_OPERATION 0
#define O3_DEV_SPF1 1
#define O3_DEV_SPF2 2
#define O3_DEV_SPF3 3
#define O3_DEV_SUSPEND 4
#define O3_DEV_RESUME 5
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