?? usbotg.h
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//Dev trans state
#define O3_DEVTRANSWIDTH 5
#define O3_DEV_TRANSIDLE 0
#define O3_DEV_SOF 1
#define O3_DEV_SOFDATA 2
#define O3_DEV_TOKEN 3
#define O3_DEV_MATCH 4
#define O3_DEV_DATA0 5
#define O3_DEV_SETUP 6
#define O3_DEV_SETUPDATA 7
#define O3_DEV_RESETUP 8
#define O3_DEV_DATA01 11
#define O3_DEV_OUT 12
#define O3_DEV_OUTDATA 13
#define O3_DEV_REOUT 14
#define O3_DEV_REIN 16
#define O3_DEV_IN 17
#define O3_DEV_INACK 18
#define O3_DEV_ACK 9
#define O3_DEV_STALL 10
#define O3_DEV_NAK 15
#define O3_DEV_ERR 19
//SIE states
#define O3_STATEWIDTH 2
#define O3_SIE_RESET 0
#define O3_SIE_OPERATION 1
#define O3_SIE_SUSPEND 2
#define O3_SIE_RESUME 3
#define O3_SIE_RESUMEDELAY 8 //240240000
#define O3_SIE_RESUMEWIDTH 3 //32
//SIE Transaction respones
#define O3_RE_ACK 2
#define O3_RE_NAK 10
#define O3_RE_STALL 0xe
#define O3_RE_TIMEOUT 0xf
//#define O3_RE_PKTOK 4'b00110000
//#define O3_RE_PKTNOTOK 4'b00100000
#define O3_RE_DATA0 3
#define O3_RE_DATA1 11
#define O3_RE_NORMAL 0
#define O3_RE_ERROR 15
//SIE Packet PID
#define O3_STRWIDTH 40 //5 chars
//SIE Transaction states
#define O3_TRANSSTATEWIDTH 5
#define O3_SIE_IDLE 0
#define O3_SIE_SENDSYNC 1
#define O3_SIE_WAIT5 2
#define O3_SIE_WAIT14 3
#define O3_SIE_LOWSPD 4
#define O3_SIE_LOWSPDSYC 5
#define O3_SIE_LASTDATA 6
#define O3_SIE_WAIT13_15 7
#define O3_SIE_PKTSENT 8
#define O3_SIE_WAIT30 9
#define O3_SIE_PRNDATA 10
#define O3_SIE_WAIT3 11
#define O3_SIE_NEXTDATA 12
#define O3_SIE_WAIT18 13
#define O3_SIE_TIMEOUT 14
#define O3_SIE_WAIT18_36 15
#define O3_SIE_STATES 16
#define O3_SIE_PKTSTATE 24
#define O3_SIE_WAIT16_34 17
#define O3_SIE_DATA0_1 18
#define O3_SIE_WAIT8 19
#define O3_SIE_DATAVALID 20
#define O3_SIE_WAIT18_21 21
#define O3_SIE_PKTOK 22
#define O3_SIE_PKTEND 23
#define O3_ISO_ENDP4 4
#define O3_ISO_ENDP5 5
#define O3_ISO_ENDP12 12
#define O3_ISO_ENDP13 13
//HNP mode, i.e., Host/Fuction Mode
#define CP_HOLD_AT_00V 0
#define CP_HOLD_AT_08V 1
#define CP_HOLD_AT_20V 2
#define CP_HOLD_AT_44V 3
#define HNP_MODE 0x00000003
#define HOST_ONLY_MODE 0x00000001
#define FUNCTION_ONLY_MODE 0x00000002
#define HW_HNP_MODE 0x00000000
#define SW_HNP_MODE 0x00000003
//clock and timer
#define t48m 20 //a cycle of clk48
#define t20ms 20000000 //20ms
// HNP register
//states in A-device
#define HNP_STATE_MASK 0x01f0
#define A_IDLE 0x0100
#define A_MASTER 0x0110
#define A_SLAVE 0x0120
#define A_WAIT_VPULSE 0x0130
#define A_WAIT_DPULSE 0x0140
#define A_SHORT_DB 0x0150
#define A_WAIT_CONN_A 0x0160
#define A_WAIT_CONN_B 0x0170
#define A_WAIT_VRISE 0x0180
#define A_SUSPEND 0x0190
#define A_WAIT_VFALL 0x01a0
#define A_VBUS_ERR 0x01b0
#define CONN_DEBOUNCE 0x01c0
#define A_WAIT_ABREQ 0x01d0
#define A_WAIT_BRST 0x01e0
//states in B-device
#define B_IDLE 0x0000
#define B_MASTER 0x0010
#define B_SLAVE 0x0020
#define B_WAIKEUP_V 0x0030
#define B_WAKEUP_D 0x0040
#define B_SHORT_DB 0x0050
#define B_WAIT_CONN_A 0x0060
#define B_WAIT_CONN_B 0x0070
#define B_WAIT_BUS_LOW 0x00A0
#define BUS_REQUEST_FLAG 0x00000002
#define BUS_DROP_FLAG 0x00000004
#define CLEAR_ERROR_FLAG 0x00000008
#define SW_DM_PD_FLAG 0x00000200
#define SW_DP_PD_FLAG 0x00000400
#define SW_PU_FLAG 0x00000800
#define MASTER_RESET_ENABLE_FLAG 0x00001000
#define SW_DISCHARGE_VBUS_FLAG 0x00002000
#define SW_PWRDOWN_VBUS_FLAG 0x00004000
#define SW_PULSE_VBUS_FLAG 0x00008000
#define SW_VBUS_ON_FLAG 0x00010000
#define IS_A_DEVICE_FLAG 0x00020000
#define IS_B_DEVICE_FLAG 0x00040000
#define CMPEN 0x00080000
#define BGEN 0x00100000
#define IS_MASTER_FLAG 0x00200000
#define IS_SLAVE_FLAG 0x00400000
#define HMP_ENABLE_FLAG 0x01000000
#define REMOTE_HMP_ENABLE_FLAG 0x02000000
#define VBUS_GTE_40V_FLAG 0x08000000
#define VBUS_GTE_20V_FLAG 0x10000000
#define VBUS_GTE_08V_FLAG 0x20000000
#define DP_DETECT_FLAG 0x40000000
//chip interrupt status bits
#define ID_CHANGE_INTERRUPT 0x00000001
#define MASTER_SLAVE_CHANGE_INT 0x00000002
#define A_SESSION_VALID_CHANGE 0x00000004
#define B_SESSION_VALID_CHANGE 0x00000008
#define VBUS_ERROR_INTERRUPT 0x00000010
#define SESSION_REQUEST_DETECT 0x00000020
#define SRP_SUCCESS_FAIL_INT 0x00000040
#define A_IDLE_B_DISC_TO_INT 0x00000080
#define A_WAIT_B_CONN_TO_INT 0x00000100
//in hardware mode register
#define VBUS_SELECT_FLAG 0x00000080
#define INSERTION_MODE_FLAG 0x00000040
#define DATA_SRP_SOURCE_FLAG 0x00000020
#define VBUS_SRP_SOURCE_FLAG 0x00000010
#define USE_EXTERNAL_PU_FLAG 0x00000008
#define HARDWARE_MNP_INV_FLAG 0xfffffffc
//wait times for OTG Timer I
#define B_WAIT_CONN_TIME 0x01000000
#define A_WAIT_DISC_TIME 0x00140000
#define A_WAIT_CONN_TIME 0x00001400
#define AWAIT_VRISE_TIME 0x0000000a
//wait times for OTG Timer II
#define SRP_VBUS_PULSE_WIDTH 0x00000020
#define SRP_D_PULSE_WIDTH 0x00000002
#define A_WAIT_B_RST_TIME 0x00000800
#define TmWtFrState 10
#define TmFrRegChg 5
#define TmFrPortStable 10
#define MHNPSTATE 0x000001f0
#define PORTREADY 0x00000103
#define PORTEN 0x00000002
#define PORT_POWERED_STATUS 0x00000100
#define PORT_CONNECT_STATUS 0x00000101
#define PORT_SUSPEND_STATUS 0x00000004
#define PORT_OVER_CURRENT 0x00000008
#define REMOTE_WAKEUP_ENABLE 0x00000010
#define A_WAIT_VRISE_TIMER 0x000000ff
#define A_WAIT_CONN_TIMER 0x0000ff00
#define A_WAIT_DISC_TIMER 0x00ff0000
#define B_WAIT_CONN_TIMER 0xff000000
#define TB_WAIT_VRISE 10
#define TB_SE0_SRP 1.5
#define TmFrResume 1
#define TB_AIDL_BDIS_MIN 3
#define TB_ACON_LDB 8
#define TB_ACON_SDB 25_000
#define TA_WAIT_VRISE 10
#define TA_WAIT_VFALL 10
#define TA_BCON_SDB 25_000
#define TA_BCON_LDB 6
#define TB_DATA_PLS 5
#define TB_VBUS_PLS 5
#define TA_VBUS_DB 9
#define TA_BDIS_ACON 3
#define TA_BIDL_ADIS_MIN 4
#define T_ID_DEBOUNCE 4
typedef struct TASK_CTRL
{
int task_address;
int task_bit;
int para_num;
int para_data[32];
int out_data;
}TASK_CTRL;
typedef struct USB_INTERRUPT
{
int intr;
int sech_int;
int connect_detect;
int resume;
int hosterr_int;
int frame_overflow;
int port_chg;
int sof_int;
int reset_complete;
int port_connect;
int hnp_int;
int is_a_int;
int masterslaveint;
int asessionvalidint;
int bsessionvalidint;
int vbuserrint;
int sessionrequestdetectedint;
int srpsuccessfailint;
int aidlebdisconnectint;
int awaitbconntimeoutint;
unsigned int etd_done;
unsigned int ep_done;
unsigned int epx_done;
unsigned int epy_done;
}USB_INTERRUPT;
typedef struct USB_PARAMETER
{
int otghf;
int hnp_state;
int ETDCompletionCodeCheck;
int ETDCompletionCodeTable[32];
}USB_PARAMETER;
#define ETD_DMA_CLIENTS NUM_ETDS
#define EP_DMA_CLIENTS 2 * NUM_EPS
typedef struct ETD_TABLE
{
int xbsa[ETD_DMA_CLIENTS];
int ybsa[ETD_DMA_CLIENTS];
int maxpacketsize[ETD_DMA_CLIENTS];
int isolength0[ETD_DMA_CLIENTS];
int isolength1[ETD_DMA_CLIENTS];
int dev;
unsigned int totalbytes;
unsigned int buffersize;
int etd_smsa[ETD_DMA_CLIENTS];
int etd_bytes_remaining[ETD_DMA_CLIENTS];
int etd_buffer_bytes_remaining[ETD_DMA_CLIENTS];
int etd_buffer_bytes_available[ETD_DMA_CLIENTS];
int etd_iso;
int etd_nextbuf;
int etd_isolen0[ETD_DMA_CLIENTS];
int etd_isolen1[ETD_DMA_CLIENTS];
}ETD_TABLE;
typedef struct EP_TABLE
{
int xbsa[EP_DMA_CLIENTS];
int ybsa[EP_DMA_CLIENTS];
int maxpacketsize[EP_DMA_CLIENTS];
int isolength0[EP_DMA_CLIENTS];
int isolength1[EP_DMA_CLIENTS];
int dev;
int fmt[EP_DMA_CLIENTS];
int totalbytes[EP_DMA_CLIENTS];
int buffersize[EP_DMA_CLIENTS];
unsigned int ep_serve;
unsigned int iso;
int ep_smsa[EP_DMA_CLIENTS];
int ep_bytes_remaining[EP_DMA_CLIENTS];
int ep_iso;
int ep_nextbuf;
int ep_isolen0[EP_DMA_CLIENTS];
int ep_isolen1[EP_DMA_CLIENTS];
}EP_TABLE;
#define NORMAL 0x0000
#define BADHANDSHAKE_AFTER_NORMAL 0x0001
#define TIMEOUT_AFTER_NORMAL 0x0002
#define BADTOKEN 0x0003
#define RETRYHANDSHAKE 0x0004
#define BADHANDSHAKE_AFTER_RETRYHANDSHAKE 0x0005
#define TIMEOUT_AFTER_RETRYHANDSHAKE 0x0006
#define BADPACKET 0x0007
#define BADTOKEN_AND_BADPACKET 0x0008
#define UNKNOWN_PID_AFTER_NORMAL 0x0009
#define UNKNOWN_PID_AFTER_RETRYHANDSHAKE 0x000d
#define EXIT_AFTER_NORMAL 0x000a
#define SKIP_TOKEN 0x000b
/* packet ids */
#define PID_DATA0 0xc3 // data0 pid
#define PID_DATA1 0x4b // data1 pid
#define PID_SETUP 0x2d // setup pid
#define PID_SOF 0xa5 // sof pid
#define PID_IN 0x69 // in pid
#define PID_OUT 0xe1 // out pid
#define PID_ACK 0xd2 // ack pid
#define PID_NAK 0x5a // nak pid
#define PID_STALL 0x1e // stall pid
#define PID_PRE 0x3c // pre amble pid
#define PID_ERR 0x00 // pid none
// CC:CompleteCode
#define CC_NOERROR 0x0000
#define CC_CRC 0x0001
#define CC_BITSTUFF 0x0002
#define CC_SEQERR 0x0003
#define CC_STALL 0x0004
#define CC_TIMEOUT 0x0005
#define CC_PIDERR 0x0006
#define CC_UNPID 0x0007
#define CC_DATAOVERRUN 0x0008
#define CC_DATAUNDERRUN 0x0009
#define CC_ACK 0x000a
#define CC_NAK 0x000b
#define CC_BUFOVERRUN 0x000c
#define CC_BUFUNDERRUN 0x000d
#define CC_NOACCESS0 0x000e //SchOverRun
#define CC_NOACCESS1 0x000f
#define FRAME90NUM 1200
#define FRAME90NUM_ST 179
#define ISO_OFFSET 143
#define FULLSPEED_OFFSET 162
#define USB_EP_ADDR(epnum, dir) ((epnum << 1) | dir)
#define USBOTG_TOP_INT_EN(a) USBOTG_TL_INT_ENABLES_ADDR |= a
#define USBOTG_TOP_SET_FUNC_MODE() USBOTG_TL_HW_MODE_ADDR &= TL_HW_MODE_MASK;USBOTG_TL_HW_MODE_ADDR |= TL_FUNC_HOST_MODE
#define USBOTG_FUNC_INT_EN(a) USBOTG_FC_SYS_INT_EN_ADDR |= a
#define USBOTG_FUNC_IS_EP_READY(ep) (USBOTG_FC_EP_READY_ADDR & (1 << ep))
#define USBOTG_FUNC_SET_EP_READY(ep) USBOTG_FC_EP_READY_ADDR = (1 << ep)
#define USBOTG_FUNC_CLR_EP_READY(ep) USBOTG_FC_FM_NUMBER_ADDR = (1 << ep)
#define USBOTG_FUNC_EN_EP(ep) USBOTG_FC_EP_ENABLES_ADDR |= (1 << ep)
#define USBOTG_FUNC_XBUF_VALID(ep) (USBOTG_FC_X_STATUS_ADDR & (1 << ep))
#define USBOTG_FUNC_SET_XBUF(ep) USBOTG_FC_X_STATUS_ADDR = (1 << ep)
#define USBOTG_FUNC_STALL_EP(ep) *((volatile unsigned *)(USBOTG_EP_BASE+ep*16)) |= 0x80000000
#define USBOTG_FUNC_TOGGLE_EP(ep) USBOTG_FC_TOGGLE_BITS_ADDR = (1 << ep)
#define USBOTG_FUNC_CLR_EP0_SETUP() *((volatile unsigned *)(USBOTG_EP_BASE+0)) &= ~0x40000000
#define USBOTG_FUNC_SET_EP_SMSA(ep,smsa) *((volatile unsigned *)(USBOTG_DMA_EPSMSA_SPACE + ep*4)) = smsa
#define USBOTG_FUNC_EP_EN_DMA(ep) USBOTG_DMA_EPENABLE_ADDR |= (1 << ep)
typedef struct tagUSB_ENDPOINT
{
unsigned int mps;
unsigned int format;
unsigned int xbsa;
unsigned int ybsa;
unsigned int bs;
}USB_ENDPOINT, *PUSB_ENDPOINT;
__inline void USBOTG_FUNC_PREPARE_EP(int epnum, int dir)
{
if(USBOTG_FUNC_XBUF_VALID(USB_EP_ADDR(epnum, dir)))
{
USBOTG_FUNC_SET_XBUF(USB_EP_ADDR(epnum, dir));
}
USBOTG_FUNC_CLR_EP_READY(USB_EP_ADDR(epnum, dir));
}
__inline void USBOTG_FUNC_SET_EP_XFER_LEN(int epnum, int dir, int len)
{
unsigned int temp;
temp = *((volatile unsigned *)(USBOTG_EP_BASE+USB_EP_ADDR(epnum, dir)*16+12));
temp &= 0xfff00000;
temp |= len;
*((volatile unsigned *)(USBOTG_EP_BASE+USB_EP_ADDR(epnum, dir)*16+12)) = temp;
}
__inline void USBOTG_FUNC_SET_EP_PID1(int epnum, int dir)
{
if(!(USBOTG_FC_TOGGLE_BITS_ADDR & (1 << USB_EP_ADDR(epnum, dir))))
{
USBOTG_FUNC_TOGGLE_EP(USB_EP_ADDR(epnum, dir));
}
}
__inline void USBOTG_FUNC_SET_EP_PID0(int epnum, int dir)
{
if((USBOTG_FC_TOGGLE_BITS_ADDR & (1 << USB_EP_ADDR(epnum, dir))))
{
USBOTG_FUNC_TOGGLE_EP(USB_EP_ADDR(epnum, dir));
}
}
__inline void USBOTG_FUNC_INIT_EP(int epnum, int dir, int mps, int format, int xbsa, int ybsa, int buffersize)
{
if (USBOTG_FUNC_IS_EP_READY(USB_EP_ADDR(epnum, dir)))
{
USBOTG_FUNC_CLR_EP_READY(USB_EP_ADDR(epnum, dir));
}
*((volatile unsigned *)(USBOTG_EP_BASE+USB_EP_ADDR(epnum, dir)*16)) = (format << 14) | (mps << 16);
*((volatile unsigned *)(USBOTG_EP_BASE+USB_EP_ADDR(epnum, dir)*16+4)) = (xbsa) | (ybsa << 16);
*((volatile unsigned *)(USBOTG_EP_BASE+USB_EP_ADDR(epnum, dir)*16+12)) = (buffersize << 21);
USBOTG_FUNC_EN_EP(USB_EP_ADDR(epnum, dir));
USBOTG_FUNC_SET_EP_READY(USB_EP_ADDR(epnum, dir));
USBOTG_FUNC_SET_EP_PID0(0, EP_IN_DIR);
USBOTG_FUNC_SET_EP_PID0(0, EP_OUT_DIR);
}
#endif//#ifndef _USB_OTG_H_
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