FR_MTS_RCV_SYNERR_BVIO,
    FR_MTS_NOT_RCV,
    FR_MTS_NOT_RCV_SYNERR,
    FR_MTS_NOT_RCV_BVIO,
    FR_MTS_NOT_RCV_SYNERR_BVIO
} Fr_MTS_state_type;

// The values are used to reference a channel on a CC
typedef enum
{
    FR_CHANNEL_A = 0,
    FR_CHANNEL_B,
    FR_CHANNEL_AB,
    FR_NO_CHANNEL
} Fr_channel_type;

// The values are used to determine which 
// slot status information is read by the Fr_get_slot_status_reg_value function
typedef enum
{
    FR_SLOT_STATUS_CURRENT = 0,
    FR_SLOT_STATUS_PREVIOUS
} Fr_slot_status_required_type;

/*
typedef enum
{
  FR_OFFSET_INC = 0,
  FR_OFFSET_DEC,
  FR_OFFSET_NOCHANGE
} Fr_offset_correction_type;

typedef enum
{
  FR_RATE_INC = 0,
  FR_RATE_DEC,
  FR_RATE_NOCHANGE
} Fr_rate_correction_type;

*/

/* Structure of this type contains configuration information
   for all receive shadow buffers */
typedef struct
{
    boolean RSBIR_A1_enable;                  // Rx shadow buffer for channel A, seg 1 - enabled?
    boolean RSBIR_A2_enable;                  // Rx shadow buffer for channel A, seg 2 - enabled?
    boolean RSBIR_B1_enable;                  // Rx shadow buffer for channel B, seg 1 - enabled?
    boolean RSBIR_B2_enable;                  // Rx shadow buffer for channel B, seg 2 - enabled?
    uint8 RSBIR_A1_buffer_number_init;        // Ch A, seg 1 - the current index of the MB header field
    uint8 RSBIR_A2_buffer_number_init;        // Ch A, seg 2 - the current index of the MB header field
    uint8 RSBIR_B1_buffer_number_init;        // Ch B, seg 1 - the current index of the MB header field
    uint8 RSBIR_B2_buffer_number_init;        // Ch B, seg 2 - the current index of the MB header field
} Fr_receive_shadow_buffers_config_type;

/* Type definition for the Fr_FIFO_range_filter_mode field
   of the Fr_FIFO_range_filter_config_type structure. */
typedef enum
{
   FR_ACCEPTANCE = 0,
   FR_REJECTION
} Fr_FIFO_range_filter_mode_type;

/* Type definition for the FIFO_range_filters_config field
   of the Fr_receive_FIFO_config structure. */
typedef struct
{
    boolean range_filter_enable;					// TRUE - Range Filter is enabled
    Fr_FIFO_range_filter_mode_type range_filter_mode;  // Acceptance or Rejection mode
    uint16 range_filter_lower_interval;			// SID0 - Slot ID - Lower interval boundary
    uint16 range_filter_upper_interval;           // SID1 - Slot ID - Upper interval boundary
} Fr_FIFO_range_filters_type;

/* Structure of this type contains configuration information
   for receive FIFO structure. */
typedef struct 
{
    Fr_channel_type FIFO_channel;	                        // FIFO channel; Channel A = FR_CHANNEL_A, channel B = FR_CHANNEL_B
    uint8 FIFO_depth;                                       // FIFO depth
    uint8 FIFO_entry_size;                                  // FIFO entry size
    uint16 FIFO_message_ID_acceptance_filter_value;         // FIFO message ID acceptance filter value
    uint16 FIFO_message_ID_acceptance_filter_mask;          // FIFO message ID acceptance filter mask
    uint16 FIFO_frame_ID_rejection_filter_value;            // FIFO frame ID rejection filter value
    uint16 FIFO_frame_ID_rejection_filter_mask;             // FIFO frame ID rejection filter mask
    Fr_FIFO_range_filters_type FIFO_range_filters_config[4];  // Reference to range filters configuration structure
    boolean FIFO_interrupt_enable;                          // FIFO interrupt enable, can be enabled also by Fr_enable_interrupts() function
} Fr_FIFO_config_type;

/* Internal FlexRay UNIFIED Driver structure
   The structure contains information about already configured FIFO storages.
   FlexRay driver stores a FIFO configuration data into this structure immediately it configures
   FIFO registers. Driver uses this structure for Data Field Offset calculation. */
typedef struct 
{
    boolean FIFO_1_used;            // The first FIFO already configured?
    Fr_channel_type FIFO_1_channel; // The first configured FIFO - FIFO A or FIFO B
    uint8 FIFO_1_depth;             // The first configured FIFO - FIFO depth
    uint8 FIFO_1_entry_size;        // The first configured FIFO - FIFO entry size
    boolean FIFO_2_used;            // The second FIFO already configured?
    Fr_channel_type FIFO_2_channel; // The second configured FIFO - FIFO A or FIFO B
    uint8 FIFO_2_depth;             // The second configured FIFO - FIFO depth
    uint8 FIFO_2_entry_size;        // The second configured FIFO - FIFO entry size
} Fr_FIFO_info_type;

/* Structure of this type contains configuration
   information for one receive buffer. */
typedef struct
{
    uint16 receive_frame_ID;                    // Receive frame ID
    Fr_channel_type receive_channel_enable;     // Receive channel enable
    boolean rx_cycle_counter_filter_enable;     // Receive cycle counter filter enable
    uint8 rx_cycle_counter_filter_value;        // Receive cycle counter filter value
    uint8 rx_cycle_counter_filter_mask;         // Receive cycle counter filter mask
    boolean rx_MB_interrupt_enable;             // Receive MB interrupt enable
} Fr_receive_buffer_config_type;

/* Type definition for the transmit_MB_buffering field of
   the Fr_transmit_buffer_config_type structure. */
typedef enum
{
    FR_SINGLE_TRANSMIT_BUFFER = 0,
    FR_DOUBLE_TRANSMIT_BUFFER
} Fr_transmit_MB_type;

/* Type definition for the transmission_mode field of
   the Fr_transmit_buffer_config_type structure. */
typedef enum
{
    FR_EVENT_TRANSMISSION_MODE = 0,
    FR_STATE_TRANSMISSION_MODE
} Fr_transmission_type;

/* Type definition for the transmission_commit_mode field
   of the Fr_transmit_buffer_config_type structure. */
typedef enum
{
    FR_STREAMING_COMMIT_MODE = 0,
    FR_IMMEDIATE_COMMIT_MODE
} Fr_transmission_commit_type;

/* Structure of this type contains configuration
   information for one transmit buffer. */
typedef struct
{
    uint16 transmit_frame_ID;								     // Transmit frame ID
    uint16 header_CRC;                                           // Header CRC
    uint8 payload_length;                                        // Payload length
    Fr_transmit_MB_type transmit_MB_buffering;                   // Transmit MB buffering
    Fr_transmission_type transmission_mode;                      // Transmission mode
    Fr_transmission_commit_type transmission_commit_mode;        // Transmission commit mode
    Fr_channel_type transmit_channel_enable;                     // Transmit channels
    boolean payload_preamble;                                    // Payload preamble
    boolean tx_cycle_counter_filter_enable;                      // Transmit cycle counter filter enable
    uint8 tx_cycle_counter_filter_value;                         // Transmit cycle counter filter value
    uint8 tx_cycle_counter_filter_mask;                          // Transmit cycle counter filter mask
    boolean tx_MB_interrupt_enable;                              // Transmit MB interrupt enable
    // If tx interrupt is enabled by tx_MB_interrupt_enable parameter, tx_MB_interrupt_transmit_side_enable determines
    // whether the interrupt will be enabled at commit side (FALSE - default) or at tranmsit side (TRUE) of the double MB
    boolean tx_MB_interrupt_transmit_side_enable;   // Used only for double buffered MB, FALSE - commit side, TRUE - transmit side
} Fr_transmit_buffer_config_type;

/* Type definition of the configured buffer */
typedef enum
{
    FR_TRANSMIT_BUFFER = 0,         // Transmit message buffer
    FR_RECEIVE_BUFFER,              // Receive message buffer
    FR_RECEIVE_FIFO,                // Receive FIFO buffer
    FR_RECEIVE_SHADOW               // Receive shadow buffer
} Fr_buffer_type;

/* Structure of this type contains configuration
   information for one physical message buffer */
typedef struct
{
    Fr_buffer_type buffer_type;           // TRANSMIT, RECEIVE, SHADOW or FIFO
    const void * const buffer_config_ptr;  // Reference to buffer configuration structure
    // Individual MB - MB index; FIFO buffers - Start index; Receive shadow buffers - no sense
    uint16 buffer_index_init;
    //uint16 data_field_offset_init;        // Data field offset init - reserved
} Fr_buffer_info_type;

/* Type definition of timer ID */
typedef enum 
{
    FR_TIMER_T1 = 0,				// Timer T1 is selected
    FR_TIMER_T2                     // Timer T2 is selected
} Fr_timer_ID_type;


/* Type definition of timer timebase */
typedef enum 
{
    FR_ABSOLUTE = 0,			    // Absolute timer timebase
    FR_RELATIVE                     // Relative timer timebase
} Fr_timer_timebase_type;

/* Type definition of timer repetition mode */
typedef enum 
{
    FR_NON_REPETITIVE = 0,          // Non repetitive timer mode
    FR_REPETITIVE                   // Repetitive timer mode
} Fr_timer_repetition_type;

/* Structure of this type contains configuration 
   information for one absolute or relative timer */
typedef struct 
{
    Fr_timer_ID_type timer_ID;                  // Timer number (T1 or T2)
    Fr_timer_timebase_type timer_type;          // Timer timebase
    Fr_timer_repetition_type timer_repetition;  // Timer repetition mode
    uint32 timer_macrotick_offset;              // Timer macrotick offset
    uint8 timer_cycle_filter_mask;              // Timer cycle filter mask, only for absolute timer
    uint8 timer_cycle_filter_value;             // Timer cycle filter value, only for absolute timer
} Fr_timer_config_type;

/* Structure of this type contains configuration information for four internal non-memory mapped slot 
   status selection register SSSR0 to SSSR3.
   If the value of any slot number is set to 0, the related slot status register provides 
   the status of the symbol window after the NIT start, and provides the status of the NIT 
   after the cycle start. */
typedef struct
{
    uint16 SSSR0_slot_number;       // Static Slot number - the number of the slot whose status will be saved in the SSR0 and SSR1
    uint16 SSSR1_slot_number;       // Static Slot number - the number of the slot whose status will be saved in the SSR2 and SSR3
    uint16 SSSR2_slot_number;       // Static Slot number - the number of the slot whose status will be saved in the SSR4 and SSR5
    uint16 SSSR3_slot_number;       // Static Slot number - the number of the slot whose status will be saved in the SSR6 and SSR7
} Fr_slot_status_config_type;

/* Type definition of Slot Status Counter ID */
typedef enum 
{
    FR_SLOT_STATUS_COUNTER_0 = 0,   // Slot Status Counter 0 is configured
    FR_SLOT_STATUS_COUNTER_1,       // Slot Status Counter 1 is configured
    FR_SLOT_STATUS_COUNTER_2,       // Slot Status Counter 2 is configured
    FR_SLOT_STATUS_COUNTER_3        // Slot Status Counter 3 is configured
} Fr_slot_status_counter_ID_type;

/* Slot Status Counter configuration - the channel related incrementing of the slot status counter */
typedef enum
{										// Slot status counter is:
    FR_SLOT_STATUS_CHANNEL_A = 0,       // Incremented by 1 if condition is fulfilled on channel A
    FR_SLOT_STATUS_CHANNEL_B,           // Incremented by 1 if condition is fulfilled on channel B
    FR_SLOT_STATUS_CHANNEL_AB_BY_1,     // Incremented by 1 if condition is fulfilled on at least one channel
    FR_SLOT_STATUS_CHANNEL_AB_BY_2      // Incremented by 2 if condition is fulfilled on both channels
                                        // Incremented by 1 if condition is fulfilled on only one channel
} Fr_slot_status_counter_channel_type;

/* Structure of this type contains configuration 
   information for one slot status counter */
typedef struct 
{
    Fr_slot_status_counter_ID_type counter_ID;      // Select one of the four internal slot counter condition register for access
    Fr_slot_status_counter_channel_type counter_configuration;  // Controls the channel related incrementing
    boolean multi_cycle_selection;                  // Define whether the counter accumulates over multiple com.cycle
    boolean valid_frame_restriction;                // Restrict the counter to receive valid frames
    boolean sync_frame_restriction;                 // Restrict the counter to receive sync frames
    boolean null_frame_restriction;                 // Restrict the counter to receive null frames
    boolean startup_frame_restriction;              // Restrict the counter to receive startup frames
    boolean syntax_error_counting;                  // Enable the counting for slots with the syntax error indicator bit set to 1
    boolean content_error_counting;                 // Enable the counting for slots with set content error indicator
    boolean boundary_violation_counting;            // Enable the counting for slots with set boundary violation indicator
    boolean transmission_conflict_counting;         // Enable the counting for slots with set transmission conflict indicator
} Fr_slot_status_counter_config_type;

/* Structure of this type contains configuration information for Media Test Symbol (MTS) */