?? s12xmmc.h
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/*******************************************************************************/
/**
Copyright (c) 2007 Freescale Semiconductor
Freescale Confidential Proprietary
\file S12XMMC.h
\brief S12XF512 Memory Mapping Control module definitions
\author Freescale Semiconductor
\author Guadalajara Applications Laboratory RTAC Americas
\author Jaime Orozco
\version 1.0
\date March/09/2007
*/
/*******************************************************************************/
/* */
/* All software, source code, included documentation, and any implied know-how */
/* are property of Freescale Semiconductor and therefore considered */
/* CONFIDENTIAL INFORMATION. */
/* */
/* This confidential information is disclosed FOR DEMONSTRATION PURPOSES ONLY. */
/* */
/* All Confidential Information remains the property of Freescale Semiconductor*/
/* and will not be copied or reproduced without the express written permission */
/* of the Discloser, except for copies that are absolutely necessary in order */
/* to fulfill the Purpose. */
/* */
/* Services performed by FREESCALE in this matter are performed AS IS and */
/* without any warranty. CUSTOMER retains the final decision relative to the */
/* total design and functionality of the end product. */
/* */
/* FREESCALE neither guarantees nor will be held liable by CUSTOMER for the */
/* success of this project. */
/* */
/* FREESCALE disclaims all warranties, express, implied or statutory including,*/
/* but not limited to, implied warranty of merchantability or fitness for a */
/* particular purpose on any hardware, software or advise supplied to the */
/* project by FREESCALE, and or any product resulting from FREESCALE services. */
/* */
/* In no event shall FREESCALE be liable for incidental or consequential */
/* damages arising out of this agreement. CUSTOMER agrees to hold FREESCALE */
/* harmless against any and all claims demands or actions by anyone on account */
/* of any damage,or injury, whether commercial, contractual, or tortuous, */
/* rising directly or indirectly as a result of the advise or assistance */
/* supplied CUSTOMER in connection with product, services or goods supplied */
/* under this Agreement. */
/* */
/*******************************************************************************/
#ifndef S12XMMC_H /*prevent duplicated includes */
#define S12XMMC_H
typedef union {
byte Byte;
struct {
byte CS0E :1; /* Chip Select Enable 0 */
byte CS1E :1; /* Chip Select Enable 1 */
byte CS2E :1; /* Chip Select Enable 2 */
byte CS3E :1; /* Chip Select Enable 3 */
byte CS0E1 :1;
byte CS1E1 :1;
byte CS2E1 :1;
byte CS3E1 :1;
} Bits;
} MMCCTL0STR;
extern volatile MMCCTL0STR _MMCCTL0 @(REG_BASE + 0x0000000A);
#define MMCCTL0 _MMCCTL0.Byte
#define MMCCTL0_CS0E _MMCCTL0.Bits.CS0E
#define MMCCTL0_CS1E _MMCCTL0.Bits.CS1E
#define MMCCTL0_CS2E _MMCCTL0.Bits.CS2E
#define MMCCTL0_CS3E _MMCCTL0.Bits.CS3E
#define MMCCTL0_CS0E1 _MMCCTL0.Bits.CS0E1
#define MMCCTL0_CS1E1 _MMCCTL0.Bits.CS1E1
#define MMCCTL0_CS2E1 _MMCCTL0.Bits.CS2E1
#define MMCCTL0_CS3E1 _MMCCTL0.Bits.CS3E1
#define MMCCTL0_CS0E_MASK 1
#define MMCCTL0_CS1E_MASK 2
#define MMCCTL0_CS2E_MASK 4
#define MMCCTL0_CS3E_MASK 8
#define MMCCTL0_CS0E1_MASK 16
#define MMCCTL0_CS1E1_MASK 32
#define MMCCTL0_CS2E1_MASK 64
#define MMCCTL0_CS3E1_MASK 128
/*** MODE - Mode Register; 0x0000000B ***/
typedef union {
byte Byte;
struct {
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte MODA :1; /* Mode Select Bit A */
byte MODB :1; /* Mode Select Bit B */
byte MODC :1; /* Mode Select Bit C */
} Bits;
struct {
byte :1;
byte :1;
byte :1;
byte :1;
byte :1;
byte grpMODx :3;
} MergedBits;
} MODESTR;
extern volatile MODESTR _MODE @(REG_BASE + 0x0000000B);
#define MODE _MODE.Byte
#define MODE_MODA _MODE.Bits.MODA
#define MODE_MODB _MODE.Bits.MODB
#define MODE_MODC _MODE.Bits.MODC
#define MODE_MODx _MODE.MergedBits.grpMODx
#define MODE_MODA_MASK 32
#define MODE_MODB_MASK 64
#define MODE_MODC_MASK 128
#define MODE_MODx_MASK 224
#define MODE_MODx_BITNUM 5
/*** GPAGE - Global Page Index Register; 0x00000010 ***/
typedef union {
byte Byte;
struct {
byte GP0 :1; /* Global Page Index Bit 0 */
byte GP1 :1; /* Global Page Index Bit 1 */
byte GP2 :1; /* Global Page Index Bit 2 */
byte GP3 :1; /* Global Page Index Bit 3 */
byte GP4 :1; /* Global Page Index Bit 4 */
byte GP5 :1; /* Global Page Index Bit 5 */
byte GP6 :1; /* Global Page Index Bit 6 */
byte :1;
} Bits;
struct {
byte grpGP :7;
byte :1;
} MergedBits;
} GPAGESTR;
extern volatile GPAGESTR _GPAGE @(REG_BASE + 0x00000010);
#define GPAGE _GPAGE.Byte
#define GPAGE_GP0 _GPAGE.Bits.GP0
#define GPAGE_GP1 _GPAGE.Bits.GP1
#define GPAGE_GP2 _GPAGE.Bits.GP2
#define GPAGE_GP3 _GPAGE.Bits.GP3
#define GPAGE_GP4 _GPAGE.Bits.GP4
#define GPAGE_GP5 _GPAGE.Bits.GP5
#define GPAGE_GP6 _GPAGE.Bits.GP6
#define GPAGE_GP _GPAGE.MergedBits.grpGP
#define GPAGE_GP0_MASK 1
#define GPAGE_GP1_MASK 2
#define GPAGE_GP2_MASK 4
#define GPAGE_GP3_MASK 8
#define GPAGE_GP4_MASK 16
#define GPAGE_GP5_MASK 32
#define GPAGE_GP6_MASK 64
#define GPAGE_GP_MASK 127
#define GPAGE_GP_BITNUM 0
/*** DIRECT - Direct Page Register; 0x00000011 ***/
typedef union {
byte Byte;
struct {
byte DP8 :1; /* Direct Page Bit 8 */
byte DP9 :1; /* Direct Page Bit 9 */
byte DP10 :1; /* Direct Page Bit 10 */
byte DP11 :1; /* Direct Page Bit 11 */
byte DP12 :1; /* Direct Page Bit 12 */
byte DP13 :1; /* Direct Page Bit 13 */
byte DP14 :1; /* Direct Page Bit 14 */
byte DP15 :1; /* Direct Page Bit 15 */
} Bits;
} DIRECTSTR;
extern volatile DIRECTSTR _DIRECT @(REG_BASE + 0x00000011);
#define DIRECT _DIRECT.Byte
#define DIRECT_DP8 _DIRECT.Bits.DP8
#define DIRECT_DP9 _DIRECT.Bits.DP9
#define DIRECT_DP10 _DIRECT.Bits.DP10
#define DIRECT_DP11 _DIRECT.Bits.DP11
#define DIRECT_DP12 _DIRECT.Bits.DP12
#define DIRECT_DP13 _DIRECT.Bits.DP13
#define DIRECT_DP14 _DIRECT.Bits.DP14
#define DIRECT_DP15 _DIRECT.Bits.DP15
#define DIRECT_DP8_MASK 1
#define DIRECT_DP9_MASK 2
#define DIRECT_DP10_MASK 4
#define DIRECT_DP11_MASK 8
#define DIRECT_DP12_MASK 16
#define DIRECT_DP13_MASK 32
#define DIRECT_DP14_MASK 64
#define DIRECT_DP15_MASK 128
/*** MMCCTL1 - S12X_MMC Control Register 1; 0x00000013 ***/
typedef union {
byte Byte;
struct {
byte ROMON :1; /* Enable FLASH or ROM in the memory map */
byte ROMHM :1; /* FLASH or ROM only in higher Half of Memory Map */
byte EROMON :1; /* Enables emulated FLASH or ROM memory in the memory map. */
byte RAMHM :1;
byte PGMIFRON :1;
byte EEIFRON :1;
byte MGROMON :1;
byte TMGRAMON :1;
} Bits;
} MMCCTL1STR;
extern volatile MMCCTL1STR _MMCCTL1 @(REG_BASE + 0x00000013);
#define MMCCTL1 _MMCCTL1.Byte
#define MMCCTL1_ROMON _MMCCTL1.Bits.ROMON
#define MMCCTL1_ROMHM _MMCCTL1.Bits.ROMHM
#define MMCCTL1_EROMON _MMCCTL1.Bits.EROMON
#define MMCCTL1_ROMON_MASK 1
#define MMCCTL1_ROMHM_MASK 2
#define MMCCTL1_EROMON_MASK 4
/*** PPAGE - Program Page Index Register; 0x00000015 ***/
typedef union {
byte Byte;
struct {
byte PIX0 :1; /* Program Page Index Bit 0 */
byte PIX1 :1; /* Program Page Index Bit 1 */
byte PIX2 :1; /* Program Page Index Bit 2 */
byte PIX3 :1; /* Program Page Index Bit 3 */
byte PIX4 :1; /* Program Page Index Bit 4 */
byte PIX5 :1; /* Program Page Index Bit 5 */
byte PIX6 :1; /* Program Page Index Bit 6 */
byte PIX7 :1; /* Program Page Index Bit 7 */
} Bits;
} PPAGESTR;
extern volatile PPAGESTR _PPAGE @(REG_BASE + 0x00000015);
#define PPAGE _PPAGE.Byte
#define PPAGE_PIX0 _PPAGE.Bits.PIX0
#define PPAGE_PIX1 _PPAGE.Bits.PIX1
#define PPAGE_PIX2 _PPAGE.Bits.PIX2
#define PPAGE_PIX3 _PPAGE.Bits.PIX3
#define PPAGE_PIX4 _PPAGE.Bits.PIX4
#define PPAGE_PIX5 _PPAGE.Bits.PIX5
#define PPAGE_PIX6 _PPAGE.Bits.PIX6
#define PPAGE_PIX7 _PPAGE.Bits.PIX7
#define PPAGE_PIX0_MASK 1
#define PPAGE_PIX1_MASK 2
#define PPAGE_PIX2_MASK 4
#define PPAGE_PIX3_MASK 8
#define PPAGE_PIX4_MASK 16
#define PPAGE_PIX5_MASK 32
#define PPAGE_PIX6_MASK 64
#define PPAGE_PIX7_MASK 128
/*** RPAGE - RAM Page Index Register; 0x00000016 ***/
typedef union {
byte Byte;
struct {
byte RP0 :1; /* RAM Page Index Bit 0 */
byte RP1 :1; /* RAM Page Index Bit 1 */
byte RP2 :1; /* RAM Page Index Bit 2 */
byte RP3 :1; /* RAM Page Index Bit 3 */
byte RP4 :1; /* RAM Page Index Bit 4 */
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