00122 <span class="preprocessor"></span><span class="preprocessor">#define SBC_SLEWRATE2           SBC_SC1</span>00123 <span class="preprocessor"></span><span class="preprocessor">#define SBC_SLEWRATE3           SBC_SC1|SBC_SC0</span>00124 <span class="preprocessor"></span><span class="preprocessor">#define SBC_SLEEP_WKPDISABLE    SBC_MODE|SBC_SC0  </span>00125 <span class="preprocessor"></span><span class="preprocessor">#define SBC_SLEEP_WKPENABLE     SBC_MODE</span>00126 <span class="preprocessor"></span>00127 00128 <span class="comment">/* IOR, Input/Output Register */</span>00129 <span class="comment">/* Write */</span>00130 <span class="preprocessor">#define SBC_HSON        0b00000100</span>00131 <span class="preprocessor"></span>        <span class="comment">/* Read */</span>00132 <span class="preprocessor">#define SBC_V2LOW       0b00001000</span>00133 <span class="preprocessor"></span><span class="preprocessor">#define SBC_HSOT        0b00000100</span>00134 <span class="preprocessor"></span><span class="preprocessor">#define SBC_VSUPLOW     0b00000010</span>00135 <span class="preprocessor"></span><span class="preprocessor">#define SBC_DEBUG       0b00000001</span>00136 <span class="preprocessor"></span>00137 00138 <span class="comment">/* WUR, Wake Up Register */</span>00139 <span class="comment">/* Write */</span>00140 <span class="preprocessor">#define SBC_LCTR3       0b00001000</span>00141 <span class="preprocessor"></span><span class="preprocessor">#define SBC_LCTR2       0b00000100</span>00142 <span class="preprocessor"></span><span class="preprocessor">#define SBC_LCTR1       0b00000010</span>00143 <span class="preprocessor"></span><span class="preprocessor">#define SBC_LCTR0       0b00000001</span>00144 <span class="preprocessor"></span><span class="comment">/* Read */</span>00145 <span class="preprocessor">#define SBC_L3WU        0b00001000</span>00146 <span class="preprocessor"></span><span class="preprocessor">#define SBC_L2WU        0b00000100</span>00147 <span class="preprocessor"></span><span class="preprocessor">#define SBC_L1WU        0b00000010</span>00148 <span class="preprocessor"></span><span class="preprocessor">#define SBC_L0WU        0b00000001</span>00149 <span class="preprocessor"></span><span class="comment">/* Control Bits */</span>00150 <span class="preprocessor">#define SBC_L0L1DISABLED    0x00</span>00151 <span class="preprocessor"></span><span class="preprocessor">#define SBC_L0L1HIGH        SBC_LCTR0</span>00152 <span class="preprocessor"></span><span class="preprocessor">#define SBC_L0L1LOW         SBC_LCTR1</span>00153 <span class="preprocessor"></span><span class="preprocessor">#define SBC_L0L1BOTH        SBC_LCTR1|SBC_LCTR0</span>00154 <span class="preprocessor"></span><span class="preprocessor">#define SBC_L2L3DISABLED    0x00</span>00155 <span class="preprocessor"></span><span class="preprocessor">#define SBC_L2L3HIGH        SBC_LCTR2</span>00156 <span class="preprocessor"></span><span class="preprocessor">#define SBC_L2L3LOW         SBC_LCTR3</span>00157 <span class="preprocessor"></span><span class="preprocessor">#define SBC_L2L3BOTH        SBC_LCTR3|SBC_LCTR2</span>00158 <span class="preprocessor"></span>00159 00160 <span class="comment">/* TIM1/2, Timing Registers */</span>00161 <span class="preprocessor">#define SBC_TIM1        0b00000000</span>00162 <span class="preprocessor"></span><span class="preprocessor">#define SBC_TIM2        0b00001000</span>00163 <span class="preprocessor"></span><span class="comment">/* TIM1 Write */</span>00164 <span class="preprocessor">#define SBC_WDW         0b00000100</span>00165 <span class="preprocessor"></span><span class="preprocessor">#define SBC_WDT1        0b00000010</span>00166 <span class="preprocessor"></span><span class="preprocessor">#define SBC_WDT0        0b00000001</span>00167 <span class="preprocessor"></span><span class="comment">/* TIM2 Write */</span>00168 <span class="preprocessor">#define SBC_CSP2        0b00000100</span>00169 <span class="preprocessor"></span><span class="preprocessor">#define SBC_CSP1        0b00000010</span>00170 <span class="preprocessor"></span><span class="preprocessor">#define SBC_CSP0        0b00000001</span>00171 <span class="preprocessor"></span><span class="comment">/* TIM1/TIM2 Read */</span>00172 <span class="preprocessor">#define SBC_CANL2VDD    0b00001000</span>00173 <span class="preprocessor"></span><span class="preprocessor">#define SBC_CANL2BAT    0b00000100</span>00174 <span class="preprocessor"></span><span class="preprocessor">#define SBC_CANL2GND    0b00000010</span>00175 <span class="preprocessor"></span><span class="preprocessor">#define SBC_TXPD        0b00000001</span>00176 <span class="preprocessor"></span><span class="comment">/* Watchdog Periods */</span>00177 <span class="preprocessor">#define SBC_WDOG_10MS           0x00</span>00178 <span class="preprocessor"></span><span class="preprocessor">#define SBC_WDOG_45MS           SBC_WDT0</span>00179 <span class="preprocessor"></span><span class="preprocessor">#define SBC_WDOG_100MS          SBC_WDT1</span>00180 <span class="preprocessor"></span><span class="preprocessor">#define SBC_WDOG_350MS          SBC_WDT1|SBC_WDT0</span>00181 <span class="preprocessor"></span><span class="preprocessor">#define SBC_WDOG_WDW_10MS       SBC_WDW</span>00182 <span class="preprocessor"></span><span class="preprocessor">#define SBC_WDOG_WDW_45MS       SBC_WDW|SBC_WDT0</span>00183 <span class="preprocessor"></span><span class="preprocessor">#define SBC_WDOG_WDW_100MS      SBC_WDW|SBC_WDT1</span>00184 <span class="preprocessor"></span><span class="preprocessor">#define SBC_WDOG_WDW_350MS      SBC_WDW|SBC_WDT1|SBC_WDT0</span>00185 <span class="preprocessor"></span><span class="comment">/* Cyclic Sense Timings */</span>00186 <span class="preprocessor">#define SBC_CYCLICSENSE_5MS     0x00</span>00187 <span class="preprocessor"></span><span class="preprocessor">#define SBC_CYCLICSENSE_9MS     SBC_CSP0</span>00188 <span class="preprocessor"></span><span class="preprocessor">#define SBC_CYCLICSENSE_18MS    SBC_CSP1</span>00189 <span class="preprocessor"></span><span class="preprocessor">#define SBC_CYCLICSENSE_37MS    SBC_CSP1|SBC_CSP0</span>00190 <span class="preprocessor"></span><span class="preprocessor">#define SBC_CYCLICSENSE_74MS    SBC_CSP2</span>00191 <span class="preprocessor"></span><span class="preprocessor">#define SBC_CYCLICSENSE_95MS    SBC_CSP2|SBC_CSP0</span>00192 <span class="preprocessor"></span><span class="preprocessor">#define SBC_CYCLICSENSE_191MS   SBC_CSP2|SBC_CSP1</span>00193 <span class="preprocessor"></span><span class="preprocessor">#define SBC_CYCLICSENSE_388MS   SBC_CSP2|SBC_CSP1|SBC_CSP0</span>00194 <span class="preprocessor"></span>00195 00196 <span class="comment">/* LPC, Low Power Control Register */</span>00197 <span class="comment">/* Write */</span>00198 <span class="preprocessor">#define SBC_LX2HS       0b00001000</span>00199 <span class="preprocessor"></span><span class="preprocessor">#define SBC_FWU         0b00000100</span>00200 <span class="preprocessor"></span><span class="preprocessor">#define SBC_CAN_INT     0b00000010</span>00201 <span class="preprocessor"></span><span class="preprocessor">#define SBC_HSAUTO          0b00000001</span>00202 <span class="preprocessor"></span><span class="comment">/* Read */</span>00203 <span class="preprocessor">#define SBC_CANH2VDD    0b00001000</span>00204 <span class="preprocessor"></span><span class="preprocessor">#define SBC_CANH2BAT    0b00000100</span>00205 <span class="preprocessor"></span><span class="preprocessor">#define SBC_CANH2GND    0b00000010</span>00206 <span class="preprocessor"></span><span class="preprocessor">#define SBC_RXPR        0b00000001</span>00207 <span class="preprocessor"></span>00208 00209 <span class="comment">/* INTR, Interrupt Register */</span>00210 <span class="comment">/* Write */</span>00211 <span class="preprocessor">#define SBC_INTVSUPLOW  0b00001000</span>00212 <span class="preprocessor"></span><span class="preprocessor">#define SBC_HSOT_V2LOW  0b00000100</span>00213 <span class="preprocessor"></span><span class="preprocessor">#define SBC_VDDTEMP     0b00000010</span>00214 <span class="preprocessor"></span><span class="preprocessor">#define SBC_CANF        0b00000001</span>00215 <span class="preprocessor"></span><span class="comment">/* Read */</span>00216 <span class="preprocessor">#define SBC_HSOT        0b00000100</span>00217 <span class="preprocessor"></span>00218 00219 00223 <span class="keywordtype">void</span> <a class="code" href="_s_b_c__driver_8c.html#a1">vfnSBC_Write</a> (UINT8 u8TXByte);00224 00226 UINT8 <a class="code" href="_s_b_c__driver_8c.html#a2">u8SBC_Read</a> (UINT8 u8TXByte);00227 00229 UINT8 <a class="code" href="_s_b_c__driver_8c.html#a3">u8SBC_StandbyMode</a> (<span class="keywordtype">void</span>);00230 00232 <span class="keywordtype">void</span> <a class="code" href="_s_b_c__driver_8c.html#a4">vfnSBC_DebugMode</a> (<span class="keywordtype">void</span>);00233 00235 <span class="keywordtype">void</span> <a class="code" href="_s_b_c__driver_8c.html#a5">vfnSBC_ClearWatchdog</a>(<span class="keywordtype">void</span>);00236 00237 00238 <span class="preprocessor">#endif </span><span class="comment">/* _SBC_H */</span>00239 00240 <span class="comment">/*******************************************************************************/</span></pre></div><!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN"><html><head></head><body><hr><table class="fs_copyright" width="100%">  <tbody>    <tr>      <td class="fs_copyright" align="left" nowrap="nowrap">Copyright&copy; 2005, <a href="http://www.freescale.com">FreescaleSemiconductor Inc.</a><br>All Rights Reserved      </td>      <td>      <div align="center"><a href="mailto:RTACGDL@freescale.com">RTACAMERICAS</a></div>      </td>      <td class="fs_copyright" align="right" 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