* Figure 33.1 CMOS: Mixed-Signal Circuit Design *

*** Top Level Netlist ***
M1 3 4 0 0 NMOSL1 L=0.5u W=3u 
M2 5 4 0 0 NMOSEKV L=0.5u W=3u 
Vds 2 0 DC 0
Vgs 4 0 DC 0
VIMTR1 2 3 0V
VIMTR2 2 5 0V

*** Control Statements ***
.option post
.DC Vds 0 3.3 .01 Vgs 0.5 3 0.5

***** MOSFET models *****

* Level 1 model nchan model 
.MODEL NMOSL1 NMOS LEVEL=1 PHI=0.97 TOX=3.4500E-09 
+ VTO=0.6 LD=0.025u RSH=510 GAMMA=0.71 LAMBDA=0.23 
+ KP=150u

*  EKV v2.6 NMOS 
*--------------- 
.MODEL NMOSEKV NMOS 
+ LEVEL  = 55     
*** Setup Parameters 
+ UPDATE = 2.6     
*** Process Related Model Parameters 
+ COX    = 3.45E-3 
+ XJ     = 0.15E-6 
*** Intrinsic Model Parameters 
+ VTO    = 0.6 
+ GAMMA  = 0.71 
+ PHI    = 0.97 
+ KP     = 150E-6 
+ E0     = 88.0E6 
+ UCRIT  = 4.5E6 
+ DL     = -0.05E-6 
+ DW     = -0.02E-6 
+ LAMBDA = 0.23 
+ LETA   = 0.28 
+ WETA   = 0.05 
+ Q0     = 280E-6 
+ LK     = 0.5E-6 
*** Substrate Current Parameters 
+ IBN    = 1.0 
+ IBA    = 200E6 
+ IBB    = 350E6 
*** Intrinsic Model Temperature Parameters 
+ TNOM   = 25.0 
+ TCV    = 1.5E-3 
+ BEX    = -1.5 
+ UCEX   = 1.7 
+ IBBT   = 0.0 
*** 1/f Noise Model Parameters 
+ KF     = 1E-27 
+ AF     = 1 
*** Short-Distance Matching Statistical Parameters (for MC simulation only) 
*+ AVTO   = 0  DEV = 10.0E-3
*+ AGAMMA = 0  DEV = 10.0E-3 
*+ AKP    = 0  DEV = 25.0E-3 
*+ AVTO   =  DEV = 15.0E-9 ! PSPICE 
*+ AGAMMA =  DEV = 15.0E-9 ! PSPICE 
*+ AKP    =  DEV = 25.0E-9 ! PSPICE 
*** Series Resistance and Area Calulation Parameters 
*+ RLEV   = 3   
+ HDIF   = 0.9E-6 
+ RSH    = 510 
*** Junction Current Parameters 
*+ ALEV   = 3    
+ JS     = 8.0E-6 
+ JSW    = 1.5E-10 
+ XTI    = 0 
+ N      = 1.5 
*** Junction Capacitances Parameters 
+ CJ     = 8.0E-4 
+ CJSW   = 3.0E-10 
+ MJ     = 0.5 
+ MJSW   = 0.3 
+ PB     = 0.9 
+ PBSW   = 0.5 
+ FC     = 0.5 
*** Gate Overlap Capacitances 
+ CGSO   = 1.5E-10 
+ CGDO   = 1.5E-10 
+ CGBO   = 4.0E-10 

.end