* Figure 33.18 CMOS: Mixed-Signal Circuit Design *
* Using the EKV model *
* Comparison between strong, moderate, and weak inversion *
* using an R-2R (W-2W) based current mirror (see text.) *

*#destroy all
*#run
*#rusage time

*plot Vbias
*#let ID1=V1#branch*1-Vref#branch
*#let ID2=V2#branch*2-Vref#branch
*#let ID3=V3#branch*4-Vref#branch
*#let ID4=V4#branch*8-Vref#branch
*#let ID5=V5#branch*16-Vref#branch
*#let ID6=V6#branch*32-Vref#branch
*#let ID7=V7#branch*64-Vref#branch
*#let ID8=V8#branch*64-Vref#branch

**#plot ID1 ID2 ID3 ID4 ID5 ID6 ID7 ID8 xlabel Reference-current-uA 
*#let Itot=V2#branch+V3#branch+V4#branch+V5#branch+V6#branch+V7#branch+V8#branch
*#plot Itot vref#branch v1#branch xlog 

*#let Er=100/Vref#branch
*#let ID1ERR=ID1*Er
*#let ID2ERR=ID2*Er
*#let ID3ERR=ID3*Er
*#let ID4ERR=ID4*Er
*#let ID5ERR=ID5*Er
*#let ID6ERR=ID6*Er
*#let ID7ERR=ID7*Er
*#let ID8ERR=ID8*Er

*#plot ID1ERR ID2ERR ID3ERR ID4ERR ID5ERR ID6ERR ID7ERR ID8ERR xlog xlabel Reference-current-uA

*** Top Level Netlist ***
Mbias Vbias Vbias 0 0 NMOS L=5u W=20u 
IREF Vb Vbias DC 1u
VREF VDD Vb DC 0
VDD VDD 0 DC 1.5

V1 VDD VD1 DC 0
V2 VDD VD2 DC 0
V3 VDD VD3 DC 0
V4 VDD VD4 DC 0
V5 VDD VD5 DC 0
V6 VDD VD6 DC 0
V7 VDD VD7 DC 0 
V8 VDD VD8 DC 0

M1  VD1 Vbias 0 0 NMOS L=5u W=20u 
M2  VD2 Vbias VS2 0 NMOS L=5u W=20u
M22 VS2 Vbias 0 0 NMOS L=5u W=40u
M3  VD3 Vbias VS3 0 NMOS L=5u W=20u 
M33 VS3 Vbias VS2 0 NMOS L=5u W=40u
M4  VD4 Vbias VS4 0 NMOS L=5u W=20u
M44 VS4 Vbias VS3 0 NMOS L=5u W=40u
M5  VD5 Vbias VS5 0 NMOS L=5u W=20u 
M55 VS5 Vbias VS4 0 NMOS L=5u W=40u
M6  VD6 Vbias VS6 0 NMOS L=5u W=20u
M66 VS6 Vbias VS5 0 NMOS L=5u W=40u
M7  VD7 Vbias VS7 0 NMOS L=5u W=20u 
M77 VS7 Vbias VS6 0 NMOS L=5u W=40u
M8 VD8 Vbias VS7 0 NMOS L=5u W=20u

*** Control Statements ***
.option post
.DC IREF .1u 100u .05u

*** NMOS EKV MOSFET Model ***************************************************
*** Level=44 in WinSPICE and ELDO, Level=55 in ADM/HSPICE, Level=5 in PSPICE, 
*** Level=EKV in Spectre
*** Lmin=0.15u Wmin=1.05u (If Scale=0.15u then Lmin=1 and Wmin=7)
*---------------
.MODEL nmos nmos
+ LEVEL=55

*** Setup Parameters
+ UPDATE=2.6

*** Process Related Model Parameters
+ COX=9.083E-3 XJ=0.15E-6

*** Intrinsic Model Parameters
+ VTO=0.4 GAMMA=0.71 PHI=0.97 KP=453E-6
+ E0=88.0E6 UCRIT=4.0E6 
+ DL=-0.05E-6 DW=-0.02E-6
+ LAMBDA = 0.30 LETA=0.28 WETA=0
+ Q0=280E-6 LK=0.5E-6

*** Substrate Current Parameters
+ IBN=1.0 IBA=200E6 IBB=350E6

*** Intrinsic Model Temperature Parameters
+ TNOM=27.0 TCV=1.5E-3 BEX=-1.5 UCEX=1.7 IBBT=0

*** 1/f Noise Model Parameters
+ KF=1E-27 AF=1

*** Series Resistance and Area Calculation Parameters
+ HDIF=0.24e-6 ACM=3 RSH=5.0 RS=1250.526
+ RD=1250.526 LDIF=0.07e-6

*** Junction Current Parameters
+ JS=1.0E-6 JSW=5.0E-11 XTI=0 N=1.5

*** Junction Capacitances Parameters
+ CJ=1.0E-3 CJSW=2.0E-10 CJGATE=5.0E-10
+ MJ=0.5 MJSW=0.3 PB=0.9 PBSW=0.9 FC=0.5

*** Gate Overlap Capacitances
+ CGSO=3.0E-10 CGDO=3.0E-10 CGBO=3.0E-11

*** SPICE Models

*** Models created by Daniel Foty.
*** (c) 2001, Gilgamesh Associates and EPFL - All rights reserved.
*** These models are provided without warranty or support.
*** These models represent a completely fictitious 0.15um process, and do
***   NOT correspond to any real silicon process.  They are provided expressly for
***   use in the examples provided in this text, and should not be used for any 
***   real silicon product design.


*** PMOS EKV MOSFET Model ***************************************************
*** Level=44 in WinSPICE and ELDO, Level=55 in ADM/HSPICE, Level=5 in PSPICE, 
*** Level=EKV in Spectre
*** Lmin=0.15u Wmin=1.05u (If Scale=0.15u then Lmin=1 and Wmin=7)
*---------------
.MODEL pmos pmos
+ LEVEL  = 55

*** Setup Parameters
+ UPDATE = 2.6

*** Process Related Model Parameters
+ COX=9.083E-3 XJ=0.15E-6

*** Intrinsic Model Parameters
+ VTO=-0.4 GAMMA=0.69 PHI=0.87 KP=92.15E-6
+ E0=51.0E6 UCRIT=18.0E6
+ DL=-0.05E-6 DW=-0.03E-6
+ LAMBDA=1.1 LETA=0.45 WETA=0
+ Q0=200E-6 LK=0.6E-6

*** Substrate Current Parameters 
+ IBN=1.0 IBA=0.0 IBB=300E6 

*** Intrinsic Model Temperature Parameters 
+ TNOM=25.0 TCV=-1.4E-3 BEX=-1.4 UCEX=2.0 IBBT=0.0 

*** 1/f Noise Model Parameters 
+ KF=1.0E-28 AF=1 

*** Series Resistance and Area Calculation Parameters   
+ HDIF=0.24E-6 ACM=3 RSH=5.0 RS=3145.263
+ RD=3145.263 LDIF=0.07e-6

*** Junction Current Parameters   
+ JS=1.0E-7 JSW=5.0E-12 XTI=0 N=1.8 

*** Junction Capacitances Parameters 
+ CJ=1.3E-3 CJSW=2.5E-10 CJGATE=5.5E-10 
+ MJ=0.5 MJSW=0.35 PB=0.9 PBSW=0.9 FC=0.5 

*** Gate Overlap Capacitances 
+ CGSO=3.2E-10 CGDO=3.2E-10 CGBO=3.0E-11

.end