* Figure 33.73 CMOS: Mixed-Signal Circuit Design *

Vdd Vdd 0 DC 1.5
Vinp Vinp 0 DC 0.75 AC 1
*Vinm Vinm 0 DC 0.75
*.DC Vinp 0.74 0.76 1u
RF Vout Vinm 100MEG
CF Vinm 0 1
.AC dec 100 100 1G
.options scale=0.15u post

*main circuit

X1 Vot1 Vob1 Vout Vdd amp
X2 Vbias1 Vbias2 Vbias3 Vbias4 Vbiasn Vbiasn2 Vbiasp Vbiasp2 Vhigh Vlow Vdd bias 
M1 Vg6 Vinp Vs12 0 NMOS L=2 W=20
M2 Vot1 Vinm Vs12 0 NMOS L=2 W=20
M3 Vs12 Vbias3 Vs3 0 NMOS L=2 W=40
M4 Vs3 Vbias4 0 0 NMOS L=2 W=40
M5 Vg6 Vbias2 Vs5 Vdd PMOS L=2 W=40
M6 Vs5 Vg6 Vdd Vdd PMOS L=2 W=40
M7 Vs8 Vg6 Vdd Vdd PMOS L=2 W=40
M8 Vob1 Vbias2 Vs8 Vdd PMOS L=2 W=40

*Start subcircuits

.subckt amp Vot1 Vob1 Vout Vdd
CC1 Vout Vgon 250f
CC2 Vout Vgop 250f
X1 Vbias1 Vbias2 Vbias3 Vbias4 Vbiasn Vbiasn2 Vbiasp Vbiasp2 Vhigh Vlow Vdd bias 
X2 Vbiasn Vhigh Vs13 Vg13 Vdd ndiff
X3 Vbiasp Vlow  Vs12 Vg12 Vdd pdiff
MON Vout Vgon 0 0 NMOS L=2 W=200
MOP Vout Vgop Vdd Vdd PMOS L=2 W=400
MC1 Vgon Vbiasp2 Vgop Vdd PMOS L=2 W=20
MC2 Vgop Vbiasn2 Vgon 0 NMOS L=2 W=10
M11 Vs12 Vob1 0 0 NMOS L=2 W=20
M12 Vgon Vg12 Vs12 0 NMOS L=2 W=20
M13 Vgop Vg12 Vs13 Vdd PMOS L=2 W=40
M14 Vs13 Vot1 Vdd Vdd PMOS L=2 W=40
M15 Vs16 Vot1 Vdd Vdd PMOS L=2 W=40
M16 Vot1 Vbias2 Vs16 Vdd PMOS L=2 W=40
M17 Vob1 Vbias3 Vs17 0 NMOS L=2 W=20
M18 Vs17 Vob1 0 0 NMOS L=2 W=20
.ends

.subckt pdiff Vbiasp Vinp Vinm Vout Vdd
M1 0 Vinp Vg4 Vdd PMOS L=2 W=40
M2 Vg4 Vbiasp Vdd Vdd PMOS L=2 W=40
M3 Vs47 Vbiasp Vdd Vdd PMOS L=2 W=40
M8 Vg7 Vbiasp Vdd Vdd PMOS L=2 W=40
M9 0 Vinm Vg7 Vdd PMOS L=2 W=40
M4 Vg5 Vg4 Vs47 Vdd PMOS L=2 W=40
M7 Vout Vg7 Vs47 Vdd PMOS L=2 W=40
M5 Vg5 Vg5 0 0 NMOS L=2 W=20
M6 Vout Vg5 0 0 NMOS L=2 W=20
.ends

.subckt ndiff Vbiasn Vinp Vinm Vout Vdd
M1 Vdd Vinp Vg3 0 NMOS L=2 W=20
M2 Vg3 Vbiasn 0 0 NMOS L=2 W=20
M9 Vdd Vinm Vg6 0 NMOS L=2 W=20
M8 Vg6 Vbiasn 0 0 NMOS L=2 W=20
M7 Vs36 Vbiasn 0 0 NMOS L=2 W=20
M3 Vg4 Vg3 Vs36 0 NMOS L=2 W=20
M6 Vout Vg6 Vs36 0 NMOS L=2 W=20
M4 Vg4 Vg4 Vdd Vdd PMOS L=2 W=40
M5 Vout Vg4 Vdd Vdd PMOS L=2 W=40
.ends

.subckt bias Vbias1 Vbias2 Vbias3 Vbias4 Vbiasn Vbiasn2 Vbiasp Vbiasp2 Vhigh Vlow Vdd 

M1 Vbiasn Vbiasn 0 0 NMOS L=2 W=20
M2 Vbiasp Vbiasn Vr 0 NMOS L=1 W=80
M3 Vbiasn Vbiasp Vdd Vdd PMOS L=2 W=40
M4 Vbiasp Vbiasp Vdd Vdd PMOS L=2 W=40
R1 Vr Vi 10k TC1=0.0024
Vi Vi 0 DC 0
M5 Vsu Vsu Vdd Vdd PMOS L=20 W=10
M6 Vsu Vsu 0 0 NMOS L=5 W=10
M7 Vdd1 Vsu Vbiasn 0 NMOS L=1 W=10
Vdd1 Vdd Vdd1 DC 0

*Generate Vbiasn2
M8 Vbiasn2 Vbiasp Vdd Vdd PMOS L=2 W=40
M9 Vbiasn2 Vbiasn2 N1 0 NMOS L=2 W=20
M10 N1 N1 0 0 NMOS L=2 W=20

*Generate Vbiasp2
M11 Vbiasp2 Vbiasn 0 0 NMOS L=2 W=20
M12 Vbiasp2 Vbiasp2 N2 Vdd PMOS L=2 W=40
M13 N2 N2 Vdd Vdd PMOS L=2 W=40

*Generate Vbias1 Vbias2
M14 Vbias2 Vbiasn 0 0 NMOS L=2 W=20
M15 Vbias2 Vbias2 Vdd Vdd PMOS L=8 W=40
M16 Vhigh Vbias1 Vdd Vdd PMOS L=2 W=40
M17 Vbias1 Vbias2 Vhigh Vdd PMOS L=2 W=40
M18 Vbias1 Vbiasn 0 0 NMOS L=2 W=20

*Generate Vbias3 Vbias4
M19 Vbias3 Vbiasp Vdd Vdd PMOS L=2 W=40
M20 Vbias3 Vbias3 0 0 NMOS L=8 W=20
M21 Vbias4 Vbiasp Vdd Vdd PMOS L=2 W=40
M22 Vbias4 Vbias3 Vlow 0 NMOS L=2 W=20
M23 Vlow Vbias4 0 0 NMOS L=2 W=20

.ends


*** SPICE Models

*** Models created by Daniel Foty.
*** (c) 2001, Gilgamesh Associates and EPFL - All rights reserved.
*** These models are provided without warranty or support.
*** These models represent a completely fictitious 0.15um process, and do
***   NOT correspond to any real silicon process.  They are provided expressly for
***   use in the examples provided in this text, and should not be used for any 
***   real silicon product design.

*** NMOS EKV MOSFET Model ***************************************************
*** Level=44 in WinSPICE and ELDO, Level=55 in ADM/HSPICE, Level=5 in PSPICE, 
*** Level=EKV in Spectre
*** Lmin=0.15u Wmin=1.05u (If Scale=0.15u then Lmin=1 and Wmin=7)
*---------------
.MODEL nmos nmos
+ LEVEL=55

*** Setup Parameters
+ UPDATE=2.6

*** Process Related Model Parameters
+ COX=9.083E-3 XJ=0.15E-6

*** Intrinsic Model Parameters
+ VTO=0.4 GAMMA=0.71 PHI=0.97 KP=453E-6
+ E0=88.0E6 UCRIT=4.0E6 
+ DL=-0.05E-6 DW=-0.02E-6
+ LAMBDA = 0.30 LETA=0.28 WETA=0
+ Q0=280E-6 LK=0.5E-6

*** Substrate Current Parameters
+ IBN=1.0 IBA=200E6 IBB=350E6

*** Intrinsic Model Temperature Parameters
+ TNOM=27.0 TCV=1.5E-3 BEX=-1.5 UCEX=1.7 IBBT=0

*** 1/f Noise Model Parameters
+ KF=1E-27 AF=1

*** Series Resistance and Area Calculation Parameters
+ HDIF=0.24e-6 ACM=3 RSH=5.0 RS=1250.526
+ RD=1250.526 LDIF=0.07e-6

*** Junction Current Parameters
+ JS=1.0E-6 JSW=5.0E-11 XTI=0 N=1.5

*** Junction Capacitances Parameters
+ CJ=1.0E-3 CJSW=2.0E-10 CJGATE=5.0E-10
+ MJ=0.5 MJSW=0.3 PB=0.9 PBSW=0.9 FC=0.5

*** Gate Overlap Capacitances
+ CGSO=3.0E-10 CGDO=3.0E-10 CGBO=3.0E-11

*** PMOS EKV MOSFET Model ***************************************************
*** Level=44 in WinSPICE and ELDO, Level=55 in ADM/HSPICE, Level=5 in PSPICE, 
*** Level=EKV in Spectre
*** Lmin=0.15u Wmin=1.05u (If Scale=0.15u then Lmin=1 and Wmin=7)
*---------------
.MODEL pmos pmos
+ LEVEL  = 55

*** Setup Parameters
+ UPDATE = 2.6

*** Process Related Model Parameters
+ COX=9.083E-3 XJ=0.15E-6

*** Intrinsic Model Parameters
+ VTO=-0.4 GAMMA=0.69 PHI=0.87 KP=92.15E-6
+ E0=51.0E6 UCRIT=18.0E6
+ DL=-0.05E-6 DW=-0.03E-6
+ LAMBDA=1.1 LETA=0.45 WETA=0
+ Q0=200E-6 LK=0.6E-6

*** Substrate Current Parameters 
+ IBN=1.0 IBA=0.0 IBB=300E6 

*** Intrinsic Model Temperature Parameters 
+ TNOM=25.0 TCV=-1.4E-3 BEX=-1.4 UCEX=2.0 IBBT=0.0 

*** 1/f Noise Model Parameters 
+ KF=1.0E-28 AF=1 

*** Series Resistance and Area Calculation Parameters   
+ HDIF=0.24E-6 ACM=3 RSH=5.0 RS=3145.263
+ RD=3145.263 LDIF=0.07e-6

*** Junction Current Parameters   
+ JS=1.0E-7 JSW=5.0E-12 XTI=0 N=1.8 

*** Junction Capacitances Parameters 
+ CJ=1.3E-3 CJSW=2.5E-10 CJGATE=5.5E-10 
+ MJ=0.5 MJSW=0.35 PB=0.9 PBSW=0.9 FC=0.5 

*** Gate Overlap Capacitances 
+ CGSO=3.2E-10 CGDO=3.2E-10 CGBO=3.0E-11

.end