library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mult1 is
generic(n11 : integer := 15;
		n22 : integer :=31);
port(a,b 		: in std_logic_vector(n11 downto 0);
	 c1  		: out std_logic_vector(n22 downto 0);
	 --x1  : out std_logic_vector(n11 downto 0);
	 load		: in std_logic;
	 clk 		: in std_logic;
	 loadout	: out std_logic);
end mult1;
architecture and1 of mult1 is
type sys is (s0,s1,s2);
begin
	process(load,clk)
	variable temp : std_logic;
	variable t    : integer range 0 to n11+2;
	variable c    : std_logic_vector(n22+1 downto 0);
	variable ys   : sys:=s0;
	variable al   : std_logic_vector(n11 downto 0);
	begin
		if clk='1' and clk'event  then
			if load='0' then
				c(n11 downto 0):=b;
				c(n22+1 downto n11+1):=conv_std_logic_vector(0,n11+2);
				--x(15 downto 0):=a;
				--x(16):='0';
				t:=n11+2;
				ys:=s2;
				al:=a;
			else
				case ys is
				when s2 =>	
					temp:=c(0);
					c(n22 downto 0):=c(n22+1 downto 1);
					c(n22+1):='0';
					t:=t-1;
						if temp='1' then
							c(n22+1 downto n11+1):=al  + c(n22+1 downto n11+1) ;
						end if;
					if t=0 then
						ys:=s1;
					end if;
				when s1 =>
					c1<=c(n22 downto 0);
					ys:=s0;
					loadout<='0';
				when s0 =>
					loadout<='1';
				end case;
			end if;
		end if;
		--x1<=x;
	end process;
end and1;