?? cic.map.rpt
字號:
+----------------------------------+-----------------+------------------------+------------------------------------------------------+
+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+---------------------------------------------+-------+
; Resource ; Usage ;
+---------------------------------------------+-------+
; Total logic elements ; 473 ;
; -- Combinational with no register ; 80 ;
; -- Register only ; 160 ;
; -- Combinational with a register ; 233 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
; -- 4 input functions ; 12 ;
; -- 3 input functions ; 169 ;
; -- 2 input functions ; 130 ;
; -- 1 input functions ; 2 ;
; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 285 ;
; -- arithmetic mode ; 188 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 136 ;
; -- asynchronous clear/load mode ; 0 ;
; ; ;
; Total registers ; 393 ;
; Total logic cells in carry chains ; 200 ;
; I/O pins ; 0 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 393 ;
; Total fan-out ; 1794 ;
; Average fan-out ; 3.54 ;
+---------------------------------------------+-------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+---------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+---------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------------+
; |CIC ; 473 (108) ; 393 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 80 (75) ; 160 (0) ; 233 (33) ; 200 (96) ; 0 (0) ; |CIC ;
; |DELAY:delay10| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 16 (16) ; 16 (16) ; 16 (16) ; 0 (0) ; |CIC|DELAY:delay10 ;
; |DELAY:delay1| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 16 (16) ; 16 (16) ; 0 (0) ; 0 (0) ; |CIC|DELAY:delay1 ;
; |DELAY:delay2| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 16 (16) ; 16 (16) ; 0 (0) ; 0 (0) ; |CIC|DELAY:delay2 ;
; |DELAY:delay3| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 16 (16) ; 16 (16) ; 0 (0) ; 0 (0) ; |CIC|DELAY:delay3 ;
; |DELAY:delay4| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 16 (16) ; 16 (16) ; 0 (0) ; 0 (0) ; |CIC|DELAY:delay4 ;
; |DELAY:delay5| ; 33 (33) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 16 (16) ; 16 (16) ; 0 (0) ; 0 (0) ; |CIC|DELAY:delay5 ;
; |DELAY:delay6| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 16 (16) ; 16 (16) ; 16 (16) ; 0 (0) ; |CIC|DELAY:delay6 ;
; |DELAY:delay7| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 16 (16) ; 16 (16) ; 16 (16) ; 0 (0) ; |CIC|DELAY:delay7 ;
; |DELAY:delay8| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 16 (16) ; 16 (16) ; 16 (16) ; 0 (0) ; |CIC|DELAY:delay8 ;
; |DELAY:delay9| ; 32 (32) ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 16 (16) ; 16 (16) ; 16 (16) ; 0 (0) ; |CIC|DELAY:delay9 ;
; |INTERPOLATER:interpolater1| ; 44 (44) ; 40 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 40 (40) ; 24 (24) ; 0 (0) ; |CIC|INTERPOLATER:interpolater1 ;
+---------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 393 ;
; Number of registers using Synchronous Clear ; 136 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 272 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+
; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |CIC|INTERPOLATER:interpolater1|count[7] ;
; 3:1 ; 96 bits ; 192 LEs ; 96 LEs ; 96 LEs ; Yes ; |CIC|INTERPOLATER:interpolater1|buffer[14] ;
; 3:1 ; 32 bits ; 64 LEs ; 32 LEs ; 32 LEs ; Yes ; |CIC|count1[30] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------+
+---------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |CIC ;
+----------------+-------+--------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+--------------------------------------------+
; N ; 5 ; Signed Integer ;
+----------------+-------+--------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: INTERPOLATER:interpolater1 ;
+----------------+-------+------------------------------------------------+
; Parameter Name ; Value ; Type ;
+----------------+-------+------------------------------------------------+
; N ; 5 ; Signed Integer ;
+----------------+-------+------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
Info: Processing started: Tue Sep 09 09:53:52 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CIC -c CIC
Info: Found 1 design units, including 1 entities, in source file CIC5.v
Info: Found entity 1: CIC
Info: Found 1 design units, including 1 entities, in source file DELAY.v
Info: Found entity 1: DELAY
Info: Found 1 design units, including 1 entities, in source file INTERPOLATER.v
Info: Found entity 1: INTERPOLATER
Info: Elaborating entity "CIC" for the top level hierarchy
Info: Elaborating entity "DELAY" for hierarchy "DELAY:delay1"
Info: Elaborating entity "INTERPOLATER" for hierarchy "INTERPOLATER:interpolater1"
Warning (10230): Verilog HDL assignment warning at INTERPOLATER.v(20): truncated value with size 32 to match size of target (8)
Info: Implemented 507 device resources after synthesis - the final resource count might be different
Info: Implemented 18 input pins
Info: Implemented 16 output pins
Info: Implemented 473 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning
Info: Allocated 127 megabytes of memory during processing
Info: Processing ended: Tue Sep 09 09:53:55 2008
Info: Elapsed time: 00:00:03
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