?? wtmpeg4ch.c
字號:
static ssize_t driver_read(struct file *file,char *buf, size_t count, loff_t *ppos){ int nRet; //int i; if(nRd==nWrt) return 0;// interruptible_sleep_on(&wq); copy_to_user(buf,StreamPool+LEAFLET*528*nRd,LEAFLET*528); nRet = nRd; nRd = (++nRd)%NR_QUEUE; //i = nWrt-nRd; //if(i<0) // i+=4; //if(i>=3) // printk("%d\n",i); return nRet;}/* * Open a video device. */static int driver_open(struct inode *inode, struct file *file){ PDEBUG("Open IP-Camera MPEG4 Capturer Driver!\n");#ifdef MOUDLE MOD_INC_USE_COUNT;#endif //MOD_INC_USE_COUNT; return 0;}/* * Last close of a video for Linux device */static int driver_release(struct inode *inode, struct file *file){#ifdef MOUDLE MOD_DEC_USE_COUNT;#endif //MOD_DEC_USE_COUNT; return 0;}static void I6400HandleFIFOFull(int irq,void * dev_id,struct pt_regs * regs){ //WORD wData; //DWORD dwData; int i; unsigned char * pData = &StreamPool[nBlock*528+16]; for(i=0;i<256;i++) *((WORD *)(pData+i*2)) = *((WORD *)dEncode); pData += 528; for(i=0;i<256;i++) *((WORD *)(pData+i*2)) = *((WORD *)dEncode); nBlock = (nBlock+2)%BLOCK; nWrt = nBlock/LEAFLET;//interrupts clear#ifdef _MCF5249_ #ifdef _HHETH_ //dwData = *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTSTAT)); *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTCLEAR))=0x00000202;#else *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTCLEAR))=0x00000404;#endif#else //dwData=*((DWORD *)(0x20+MCF_MBAR)); //dwData &=0x77f77777; *((DWORD *)(0x20+MCF_MBAR))&=0x77f77777;#endif I6400WriteReg(User4,++wLoop);// if(nWrt != nRd && waitqueue_active(&wq))// wake_up_interruptible(&wq); return;}static struct file_operations driver_fops={ NULL, NULL,/* seek */ driver_read, NULL, /* write */ NULL, /* readdir */ NULL, /* poll */ NULL, /* ioctl */ NULL, /* mmap */ driver_open, NULL, /* flush */ driver_release, NULL};/* * Initialise video for linux */ int wtmpeg4ch_init(void){ int result; int major;#ifndef _MCF5249_ DWORD dwData; DWORD PB4_5;#endif#ifdef MOUDLE SET_MODULE_OWNER(&driver_fops);#endif major=register_chrdev(DEVICEMAJOR,"MPG4CAP", &driver_fops); if(major< 0) { PDEBUG("MPG4CAP:Uunable to get major!\n"); return -EIO; } //udelay(100000);#ifdef _MCF5249_ //initial MCF5249 chip select 1 register //MCFWriteReg(MCFSIM_CSAR1, 0x30000000); //MCFWriteReg(MCFSIM_CSCR1,0x00003d80); //MCFWriteReg(MCFSIM_CSMR1,0x00FF0021); *((DWORD*)(MCF_MBAR+MCFSIM_CSAR1))=0x30000000; *((WORD*)(MCF_MBAR+MCFSIM_CSCR1))=WAITLENTH(ta_wait); *((DWORD*)(MCF_MBAR+MCFSIM_CSMR1))=0x00ff0021; #else //initial chip select register(5272) M5272WriteReg(0x54,0xfffff806); //0xffff802 0 wait; 0xfffff806 0x01 wait state,0xfffff80e 3wait states M5272WriteReg(0x50,0x01000201); #endif PDEBUG("Initial CS Register Finish!\n"); #ifdef _MCF5249_ #ifndef _HHETH_ //setup gpio 9 -- PB4(5272) //setup gpio 15 -- PB5(5272) //setup gpio 21 -- PB6(5272) *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOFUNC))|= 0x00208200;//gpio-func *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOENABLE))|= 0x00208200;//gpio-en *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOWRITE)) |= 0x00208200;//gpio-out:high at startup //setup gpio 56 -- PB7(5272) *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIO1FUNC))|= 0x01000000;//gpio1-func *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIO1ENABLE))|= 0x01000000;//gpio1-en, *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIO1WRITE))|= 0x01000000;//gpio1-en,1:high at startup #endif#ifdef _HHETH_ //setup gpio 3 -- PB4(5272) //setup gpio 21 -- PB6(5272) //setup gpio 23 -- PB7(5272) *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOFUNC))|= 0x00a00008;//gpio-func *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOENABLE))|= 0x00a00008;//gpio-en *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOWRITE)) |= 0x00a00008;//gpio-out:high at startup //setup gpio 55 -- PB5(5272) *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIO1FUNC))|= 0x00800000;//gpio1-func *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIO1ENABLE))|= 0x00800000;//gpio1-en, *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIO1WRITE))|= 0x00800000;//gpio1-en,1:high at startup #endif #else //*** New added (for 5272) PB4_5=M5272ReadReg(0x88)&0xfffff0ff; M5272WriteReg(0x88,PB4_5); //**#endif ///////////////////////////////////////////// I6400WriteReg(User4,0); //Register interrupts result=request_irq(IrqID,I6400HandleFIFOFull,SA_INTERRUPT,"MPG4CAP",NULL); if(result) { PDEBUG("MPG4CAP:Can't get assigned irq %i\n",IrqID); return 1; } else PDEBUG("Request Interrupts successfully!\n"); //config interrupts registers#ifdef _MCF5249_#ifdef _HHETH_ //gpio1 //set INT 1 -- level 7 enable //dwData = *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOFUNC)); *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOFUNC))&=0xfffffffd; //dwData = *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTENABLE)); //h-l interrupts *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTENABLE))|=0x0000200; // dwData = *((DWORD*)(MCF_MBAR2+MCFSIM2_INTLEVEL5)); *((DWORD*)(MCF_MBAR2+MCFSIM2_INTLEVEL5))|=0x00000070;#else //gpio2 //set INT 1 -- level 7 enable //dwData = *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOFUNC)); *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOFUNC))&=0xfffffffb; //dwData = *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTENABLE)); //h-l interrupts *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTENABLE))|=0x0000400; //dwData = *((DWORD*)(MCF_MBAR2+MCFSIM2_INTLEVEL5)); *((DWORD*)(MCF_MBAR2+MCFSIM2_INTLEVEL5))|=0x00000700; #endif #else dwData=M5272ReadReg(0x20); dwData&=0xff0fffff; dwData|=0x00d00000; M5272WriteReg(0x20,dwData); dwData=M5272ReadReg(0x38); dwData|=0x20000000; M5272WriteReg(0x38,dwData);#endif // PDEBUG("interrupts setup end\n"); StreamPool = (unsigned char *)kmalloc(sizeof(char)*528*BLOCK,GFP_KERNEL); if(StreamPool == NULL) { PDEBUG("MPG4CAP:Allocate Memory error!\n"); return -1; } //interrupts clear#ifdef _MCF5249_ #ifdef _HHETH_ //dwData = *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTSTAT)); *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTCLEAR))=0x00000202;#else *((DWORD*)(MCF_MBAR2+MCFSIM2_GPIOINTCLEAR))=0x00000404;#endif#else //dwData=*((DWORD *)(0x20+MCF_MBAR)); //dwData &=0x77f77777; *((DWORD *)(0x20+MCF_MBAR))&=0x77f77777;#endif PDEBUG("Ime6400 driver init OK\n"); return 0;}#ifdef MODULEvoid wtmpeg4ch_cleanup(void){ kfree(StreamPool); freeirq(IrqID,NULL); unregister_chrdev(DEVICEMAJOR, "MPG4CAP"); PDEBUG("release MPG4CAP!!!\n"); }module_init(wtmpeg4ch_init);module_exit(wtmpeg4ch_cleanup);#endif?? 快捷鍵說明
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