/** * @file IxEthAccCommon.c * * @author Intel Corporation * @date 12-Feb-2002 * * @brief This file contains the implementation common support routines for the component * * Design Notes: * * @par * IXP400 SW Release version 2.0 * * -- Copyright Notice -- * * @par * Copyright 2001-2005, Intel Corporation. * All rights reserved. * * @par * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright *    notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright *    notice, this list of conditions and the following disclaimer in the *    documentation and/or other materials provided with the distribution. * 3. Neither the name of the Intel Corporation nor the names of its contributors *    may be used to endorse or promote products derived from this software *    without specific prior written permission. * * @par * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. * * @par * -- End of Copyright Notice -- *//* * Component header files */#include "IxOsal.h"#include "IxEthAcc.h"#include "IxEthDB.h"#include "IxNpeMh.h"#include "IxEthDBPortDefs.h"#include "IxFeatureCtrl.h"#include "IxEthAcc_p.h"#include "IxEthAccQueueAssign_p.h"#include "IxEthAccDataPlane_p.h"#include "IxEthAccMii_p.h"/** * @addtogroup IxEthAccPri *@{ */extern IxEthAccInfo   ixEthAccDataInfo;/** * * @brief Maximum number of RX queues set to be the maximum number * of traffic calsses. * */#define IX_ETHACC_MAX_RX_QUEUES \      (IX_ETH_DB_QOS_TRAFFIC_CLASS_7_RX_QUEUE_PROPERTY \      - IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY \      + 1)/** * * @brief Maximum number of 128 entry RX queues * */#define IX_ETHACC_MAX_LARGE_RX_QUEUES 4/** * * @brief Data structure template for Default RX Queues * */IX_ETH_ACC_PRIVATEIxEthAccQregInfo ixEthAccQmgrRxDefaultTemplate =  {    IX_ETH_ACC_RX_FRAME_ETH_Q, 	     /**< Queue ID */    "Eth Rx Q",    ixEthRxFrameQMCallback,          /**< Functional callback */    (IxQMgrCallbackId) 0,	     /**< Callback tag	      */    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */    TRUE,			     /**< Enable Q notification at startup */    IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback   */    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */    IX_QMGR_Q_WM_LEVEL1,	     /**< Q High water mark - needed by NPE */  };/** * * @brief Data structure template for Small RX Queues * */IX_ETH_ACC_PRIVATEIxEthAccQregInfo ixEthAccQmgrRxSmallTemplate =  {    IX_ETH_ACC_RX_FRAME_ETH_Q, 	     /**< Queue ID */    "Eth Rx Q",    ixEthRxFrameQMCallback,          /**< Functional callback */    (IxQMgrCallbackId) 0,	     /**< Callback tag	      */    IX_QMGR_Q_SIZE64,		     /**< Allocate Smaller Q */    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */    TRUE,			     /**< Enable Q notification at startup */    IX_ETH_ACC_RX_FRAME_ETH_Q_SOURCE,/**< Q Condition to drive callback   */    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */    IX_QMGR_Q_WM_LEVEL1,	     /**< Q High water mark - needed by NPE */  };/** * * @brief Data structure used to register & initialize the Queues * */IX_ETH_ACC_PRIVATEIxEthAccQregInfo ixEthAccQmgrStaticInfo[]={  {    IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q,    "Eth Rx Fr Q 1",    ixEthRxFreeQMCallback,    (IxQMgrCallbackId) IX_ETH_PORT_1,    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */    FALSE,			     /**< Disable Q notification at startup */    IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q_SOURCE, /**< Q Condition to drive callback  */    IX_QMGR_Q_WM_LEVEL0, 	     /***< Q Low water mark */    IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */  },  {    IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q,    "Eth Rx Fr Q 2",    ixEthRxFreeQMCallback,    (IxQMgrCallbackId) IX_ETH_PORT_2,    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */    FALSE,			     /**< Disable Q notification at startup */    IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q_SOURCE,  /**< Q Condition to drive callback  */    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */    IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */  },#ifdef __ixp46X  {    IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q,    "Eth Rx Fr Q 3",    ixEthRxFreeQMCallback,    (IxQMgrCallbackId) IX_ETH_PORT_3,    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */    FALSE,			     /**< Disable Q notification at startup */    IX_ETH_ACC_RX_FREE_BUFF_ENET2_Q_SOURCE,  /**< Q Condition to drive callback  */    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */    IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */  },#endif  {     IX_ETH_ACC_TX_FRAME_ENET0_Q,    "Eth Tx Q 1",     ixEthTxFrameQMCallback,     (IxQMgrCallbackId) IX_ETH_PORT_1,    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */    FALSE,			     /**< Disable Q notification at startup */    IX_ETH_ACC_TX_FRAME_ENET0_Q_SOURCE,	 /**< Q Condition to drive callback  */    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */    IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */  },  {     IX_ETH_ACC_TX_FRAME_ENET1_Q,    "Eth Tx Q 2",     ixEthTxFrameQMCallback,     (IxQMgrCallbackId) IX_ETH_PORT_2,    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */    FALSE,			     /**< Disable Q notification at startup */    IX_ETH_ACC_TX_FRAME_ENET1_Q_SOURCE,	     /**< Q Condition to drive callback  */    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */    IX_QMGR_Q_WM_LEVEL64,	     /**< Q High water mark */  },#ifdef __ixp46X  {     IX_ETH_ACC_TX_FRAME_ENET2_Q,    "Eth Tx Q 3",     ixEthTxFrameQMCallback,     (IxQMgrCallbackId) IX_ETH_PORT_3,    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */    IX_QMGR_Q_ENTRY_SIZE1,	     /** Queue Entry Sizes - all Q entries are single ord entries   */    FALSE,			     /** Disable Q notification at startup */    IX_ETH_ACC_TX_FRAME_ENET2_Q_SOURCE,	     /** Q Condition to drive callback  */    IX_QMGR_Q_WM_LEVEL0, 	     /* No queues use almost empty */    IX_QMGR_Q_WM_LEVEL64,	      /** Q High water mark - needed used  */  },#endif  {     IX_ETH_ACC_TX_FRAME_DONE_ETH_Q,    "Eth Tx Done Q",     ixEthTxFrameDoneQMCallback,     (IxQMgrCallbackId) 0,    IX_QMGR_Q_SIZE128,		     /**< Allocate Max Size Q */    IX_QMGR_Q_ENTRY_SIZE1,	     /**< Queue Entry Sizes - all Q entries are single word entries   */    TRUE,			     /**< Enable Q notification at startup */    IX_ETH_ACC_TX_FRAME_DONE_ETH_Q_SOURCE, /**< Q Condition to drive callback  */    IX_QMGR_Q_WM_LEVEL0, 	     /**< Q Low water mark */    IX_QMGR_Q_WM_LEVEL2,	     /**< Q High water mark - needed by NPE */  },  {  /* Null Termination entry      */     (IxQMgrQId)0,     (char *) NULL,     (IxQMgrCallback) NULL,     (IxQMgrCallbackId) 0,     0,     0,     0,     0,     0,     0  }};/** * * @brief Data structure used to register & initialize the Queues * * The structure will be filled at run time depending on the NPE * image already loaded and the QoS configured in ethDB. * */IX_ETH_ACC_PRIVATEIxEthAccQregInfo ixEthAccQmgrRxQueuesInfo[IX_ETHACC_MAX_RX_QUEUES+1]={  {  /* PlaceHolder for rx queues      * depending on the QoS configured      */     (IxQMgrQId)0,     (char *) NULL,     (IxQMgrCallback) NULL,     (IxQMgrCallbackId) 0,     0,     0,     0,     0,     0,     0  },  {  /* PlaceHolder for rx queues      * depending on the QoS configured      */     (IxQMgrQId)0,     (char *) NULL,     (IxQMgrCallback) NULL,     (IxQMgrCallbackId) 0,     0,     0,     0,     0,     0,     0  },  {  /* PlaceHolder for rx queues      * depending on the QoS configured      */     (IxQMgrQId)0,     (char *) NULL,     (IxQMgrCallback) NULL,     (IxQMgrCallbackId) 0,     0,     0,     0,     0,     0,     0  },  {  /* PlaceHolder for rx queues      * depending on the QoS configured      */     (IxQMgrQId)0,     (char *) NULL,     (IxQMgrCallback) NULL,     (IxQMgrCallbackId) 0,     0,     0,     0,     0,     0,     0  },  {  /* PlaceHolder for rx queues      * depending on the QoS configured      */     (IxQMgrQId)0,     (char *) NULL,     (IxQMgrCallback) NULL,     (IxQMgrCallbackId) 0,     0,     0,     0,     0,     0,     0  },  {  /* PlaceHolder for rx queues      * depending on the QoS configured      */      (IxQMgrQId)0,     (char *) NULL,     (IxQMgrCallback) NULL,     (IxQMgrCallbackId) 0,     0,     0,     0,     0,     0,     0  },  {  /* PlaceHolder for rx queues      * depending on the QoS configured      */     (IxQMgrQId)0,     (char *) NULL,     (IxQMgrCallback) NULL,     (IxQMgrCallbackId) 0,     0,     0,     0,     0,     0,     0  },  {  /* PlaceHolder for rx queues      * depending on the QoS configured      */     (IxQMgrQId)0,     (char *) NULL,     (IxQMgrCallback) NULL,     (IxQMgrCallbackId) 0,     0,     0,     0,     0,     0,     0  },  {  /* Null Termination entry      */     (IxQMgrQId)0,     (char *) NULL,     (IxQMgrCallback) NULL,     (IxQMgrCallbackId) 0,     0,     0,     0,     0,     0,     0  }};/* forward declarations */IX_ETH_ACC_PRIVATE IxEthAccStatusixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes);/** * @fn ixEthAccQMgrQueueSetup(void) * * @brief Setup one queue and its event, and register the callback required * by this component to the QMgr * * @internal */IX_ETH_ACC_PRIVATE IxEthAccStatusixEthAccQMgrQueueSetup(IxEthAccQregInfo *qInfoDes){    /*     * Configure each Q.     */    if ( ixQMgrQConfig( qInfoDes->qName,			qInfoDes->qId,			qInfoDes->qSize,			qInfoDes->qWords) != IX_SUCCESS)    {	return IX_ETH_ACC_FAIL;    }    if ( ixQMgrWatermarkSet( qInfoDes->qId,			     qInfoDes->AlmostEmptyThreshold,			     qInfoDes->AlmostFullThreshold			     ) != IX_SUCCESS)    {	return IX_ETH_ACC_FAIL;    }    /*     * Set dispatcher priority.     */    if ( ixQMgrDispatcherPrioritySet( qInfoDes->qId,				      IX_ETH_ACC_QM_QUEUE_DISPATCH_PRIORITY)	 != IX_SUCCESS)    {	return IX_ETH_ACC_FAIL;    }    /*     * Register callbacks for each Q.     */    if ( ixQMgrNotificationCallbackSet(qInfoDes->qId,				       qInfoDes->qCallback,				       qInfoDes->callbackTag)	 != IX_SUCCESS )    {	return IX_ETH_ACC_FAIL;    }    /*     * Set notification condition for Q     */    if ( qInfoDes->qNotificationEnableAtStartup == TRUE )    {	if (   ixQMgrNotificationEnable(qInfoDes->qId,					qInfoDes->qConditionSource)	       != IX_SUCCESS )	{	    return IX_ETH_ACC_FAIL;	}    }    return(IX_ETH_ACC_SUCCESS);}/** * @fn ixEthAccQMgrQueuesConfig(void) * * @brief Setup all the queues and register all callbacks required * by this component to the QMgr * * The RxFree queues, tx queues, rx queues are configured statically * * Rx queues configuration is driven by QoS setup. * Many Rx queues may be required when QoS is enabled (this depends * on IxEthDB setup and the images being downloaded). The configuration * of the rxQueues is done in many steps as follows: * * @li select all Rx queues as configured by ethDB for all ports * @li sort the queues by traffic class * @li build the priority dependency for all queues * @li fill the configuration for all rx queues * @li configure all statically configured queues * @li configure all dynamically configured queues * * @param none * * @return IxEthAccStatus * * @internal */IX_ETH_ACC_PUBLICIxEthAccStatus ixEthAccQMgrQueuesConfig(void){    struct    {	int npeCount;	UINT32 npeId;	IxQMgrQId qId;	IxEthDBProperty trafficClass;    } rxQueues[IX_ETHACC_MAX_RX_QUEUES];    UINT32 rxQueue = 0;    UINT32 rxQueueCount = 0;    IxQMgrQId ixQId =IX_QMGR_MAX_NUM_QUEUES;    IxEthDBStatus ixEthDBStatus = IX_ETH_DB_SUCCESS;    IxEthDBPortId ixEthDbPortId = 0;    IxEthAccPortId ixEthAccPortId = 0;    UINT32 ixNpeId = 0;    UINT32 ixHighestNpeId = 0;    UINT32 sortIterations = 0;    IxEthAccStatus ret = IX_ETH_ACC_SUCCESS;    IxEthAccQregInfo *qInfoDes = NULL;    IxEthDBProperty ixEthDBTrafficClass = IX_ETH_DB_QOS_TRAFFIC_CLASS_0_RX_QUEUE_PROPERTY;    IxEthDBPropertyType ixEthDBPropertyType = IX_ETH_DB_INTEGER_PROPERTY;    UINT32 ixEthDBParameter = 0;    BOOL completelySorted = FALSE;    /* Fill the corspondance between ports and queues     * This defines the mapping from port to queue Ids.     */    ixEthAccPortData[IX_ETH_PORT_1].ixEthAccRxData.rxFreeQueue	= IX_ETH_ACC_RX_FREE_BUFF_ENET0_Q;    ixEthAccPortData[IX_ETH_PORT_2].ixEthAccRxData.rxFreeQueue	= IX_ETH_ACC_RX_FREE_BUFF_ENET1_Q;