*/#define IX_NPE_A_RXDESCRIPTOR_PCURRMBUFDATA_OFFSET  24/** * @def IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET * * @brief ATM Descriptor structure offset for Receive Descriptor Next MBuf Pointer * * Pointer to the next MBuf in a chain of MBufs. */#define IX_NPE_A_RXDESCRIPTOR_PNEXTMBUF_OFFSET      28/** * @def IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET * * @brief ATM Descriptor structure offset for Receive Descriptor Total Length * * Total number of bytes written to the chain of MBufs by the NPE */#define IX_NPE_A_RXDESCRIPTOR_TOTALLENGTH_OFFSET    32/** * @def IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET * * @brief ATM Descriptor structure offset for Receive Descriptor AAL5 CRC Residue * * Current CRC value for a PDU */#define IX_NPE_A_RXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 36/** * @def IX_NPE_A_RXDESCRIPTOR_SIZE * * @brief ATM Descriptor structure offset for Receive Descriptor Size * * The size of the Receive descriptor */#define IX_NPE_A_RXDESCRIPTOR_SIZE                  40/** * @def IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET * * @brief ATM Descriptor structure offset for Transmit Descriptor Port * * Port identifier. */#define IX_NPE_A_TXDESCRIPTOR_PORT_OFFSET            0/** * @def IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET * * @brief ATM Descriptor structure offset for Transmit Descriptor RSVD */#define IX_NPE_A_TXDESCRIPTOR_RSVD_OFFSET            1/** * @def IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET * * @brief ATM Descriptor structure offset for Transmit Descriptor Current MBuf Length * * TX - Initialized by the XScale to the number of bytes in the current MBuf data buffer. * The NPE decrements this field for every transmitted cell.  Thus, when the NPE writes a * descriptor the TxDone queue, this field will equal zero. */#define IX_NPE_A_TXDESCRIPTOR_CURRMBUFLEN_OFFSET     2/** * @def IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET * @brief ATM Descriptor structure offset for Transmit Descriptor ATM Header */#define IX_NPE_A_TXDESCRIPTOR_ATMHEADER_OFFSET       4/** * @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET * * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf chain */#define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFF_OFFSET      8/** * @def IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET * * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the current MBuf Data * * Pointer to the next byte to be read or next free location to be written. */#define IX_NPE_A_TXDESCRIPTOR_PCURRMBUFDATA_OFFSET  12/** * @def IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET * * @brief ATM Descriptor structure offset for Transmit Descriptor Pointer to the Next MBuf chain */#define IX_NPE_A_TXDESCRIPTOR_PNEXTMBUF_OFFSET      16/** * @def IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET * * @brief ATM Descriptor structure offset for Transmit Descriptor Total Length * * Total number of bytes written to the chain of MBufs by the NPE */#define IX_NPE_A_TXDESCRIPTOR_TOTALLENGTH_OFFSET    20/** * @def IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET * * @brief ATM Descriptor structure offset for Transmit Descriptor AAL5 CRC Residue * * Current CRC value for a PDU */#define IX_NPE_A_TXDESCRIPTOR_AAL5CRCRESIDUE_OFFSET 24/** * @def IX_NPE_A_TXDESCRIPTOR_SIZE * * @brief ATM Descriptor structure offset for Transmit Descriptor Size */#define IX_NPE_A_TXDESCRIPTOR_SIZE                  28/** * @def IX_NPE_A_CHAIN_DESC_COUNT_MAX * * @brief Maximum number of chained MBufs that can be chained together */#define IX_NPE_A_CHAIN_DESC_COUNT_MAX            256/* *  Definition of the ATM cell header * * This would most conviently be defined as the bit field shown below. * Endian portability prevents this, therefore a set of macros * are defined to access the fields within the cell header assumed to * be passed as a UINT32. * * Changes to field sizes or orders must be reflected in the offset * definitions above. * *    typedef struct *    { *       unsigned int gfc:4; *       unsigned int vpi:8; *       unsigned int vci:16; *       unsigned int pti:3; *       unsigned int clp:1; *    } IxNpeA_AtmCellHeader; * *//** Mask to acess GFC */#define GFC_MASK        0xf0000000/** return GFC from ATM cell header */#define IX_NPE_A_ATMCELLHEADER_GFC_GET( header ) \(((header) & GFC_MASK) >> 28)/** set GFC into ATM cell header */#define IX_NPE_A_ATMCELLHEADER_GFC_SET( header,gfc ) \do { \    (header) &= ~GFC_MASK; \    (header) |= (((gfc) << 28) & GFC_MASK); \} while(0)/** Mask to acess VPI */#define VPI_MASK        0x0ff00000/** return VPI from ATM cell header */#define IX_NPE_A_ATMCELLHEADER_VPI_GET( header ) \(((header) & VPI_MASK) >> 20)/** set VPI into ATM cell header */#define IX_NPE_A_ATMCELLHEADER_VPI_SET( header, vpi ) \do { \    (header) &= ~VPI_MASK; \    (header) |= (((vpi) << 20) & VPI_MASK); \} while(0)/** Mask to acess VCI */#define VCI_MASK        0x000ffff0/** return VCI from ATM cell header */#define IX_NPE_A_ATMCELLHEADER_VCI_GET( header ) \(((header) & VCI_MASK) >> 4)/** set VCI into ATM cell header */#define IX_NPE_A_ATMCELLHEADER_VCI_SET( header, vci ) \do { \    (header) &= ~VCI_MASK; \    (header) |= (((vci) << 4) & VCI_MASK); \} while(0)/** Mask to acess PTI */#define PTI_MASK        0x0000000e/** return PTI from ATM cell header */#define IX_NPE_A_ATMCELLHEADER_PTI_GET( header ) \(((header) & PTI_MASK) >> 1)/** set PTI into ATM cell header */#define IX_NPE_A_ATMCELLHEADER_PTI_SET( header, pti ) \do { \    (header) &= ~PTI_MASK; \    (header) |= (((pti) << 1) & PTI_MASK); \} while(0)/** Mask to acess CLP */#define CLP_MASK        0x00000001/** return CLP from ATM cell header */#define IX_NPE_A_ATMCELLHEADER_CLP_GET( header ) \((header) & CLP_MASK)/** set CLP into ATM cell header */#define IX_NPE_A_ATMCELLHEADER_CLP_SET( header, clp ) \do { \    (header) &= ~CLP_MASK; \    (header) |= ((clp) & CLP_MASK); \} while(0)/** Definition of the Rx bitfield** This would most conviently be defined as the bit field shown below.* Endian portability prevents this, therefore a set of macros* are defined to access the fields within the rxBitfield assumed to* be passed as a UINT32.** Changes to field sizes or orders must be reflected in the offset* definitions above.** Rx bitfield*    struct*    {   IX_NPEA_RXBITFIELD(*        unsigned int status:1,*        unsigned int port:7,*        unsigned int vcId:8,*        unsigned int currMbufSize:16);*    } rxBitField;**//** Mask to acess the rxBitField status */#define STATUS_MASK     0x80000000/** return the rxBitField status */#define IX_NPE_A_RXBITFIELD_STATUS_GET( rxbitfield ) \(((rxbitfield) & STATUS_MASK) >> 31)/** set the rxBitField status */#define IX_NPE_A_RXBITFIELD_STATUS_SET( rxbitfield, status ) \do { \    (rxbitfield) &= ~STATUS_MASK; \    (rxbitfield) |= (((status) << 31) & STATUS_MASK); \} while(0)/** Mask to acess the rxBitField port */#define PORT_MASK       0x7f000000/** return the rxBitField port */#define IX_NPE_A_RXBITFIELD_PORT_GET( rxbitfield ) \(((rxbitfield) & PORT_MASK) >> 24)/** set the rxBitField port */#define IX_NPE_A_RXBITFIELD_PORT_SET( rxbitfield, port ) \do { \    (rxbitfield) &= ~PORT_MASK; \    (rxbitfield) |= (((port) << 24) & PORT_MASK); \} while(0)/** Mask to acess the rxBitField vcId */#define VCID_MASK       0x00ff0000/** return the rxBitField vcId */#define IX_NPE_A_RXBITFIELD_VCID_GET( rxbitfield ) \(((rxbitfield) & VCID_MASK) >> 16)/** set the rxBitField vcId */#define IX_NPE_A_RXBITFIELD_VCID_SET( rxbitfield, vcid ) \do { \    (rxbitfield) &= ~VCID_MASK; \    (rxbitfield) |= (((vcid) << 16) & VCID_MASK); \} while(0)/** Mask to acess the rxBitField mbuf size */#define CURRMBUFSIZE_MASK       0x0000ffff/** return the rxBitField mbuf size */#define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_GET( rxbitfield ) \((rxbitfield) & CURRMBUFSIZE_MASK)/** set the rxBitField mbuf size */#define IX_NPE_A_RXBITFIELD_CURRMBUFSIZE_SET( rxbitfield, currmbufsize ) \do { \    (rxbitfield) &= ~CURRMBUFSIZE_MASK; \    (rxbitfield) |= ((currmbufsize) & CURRMBUFSIZE_MASK); \} while(0)/** * @brief Tx Descriptor definition */typedef struct{    UINT8 port;				/**< Tx Port number */    UINT8 aalType; 			/**< AAL Type */    UINT16 currMbufLen;			/**< mbuf length */    UINT32 atmCellHeader;		/**< ATM cell header */    IX_OSAL_MBUF *pCurrMbuf;	        /**< pointer to mbuf */    unsigned char *pCurrMbufData;	/**< Pointer to mbuf->dat */    IX_OSAL_MBUF *pNextMbuf;		/**< Pointer to next mbuf */    UINT32  totalLen;			/**< Total Length */    UINT32  aal5CrcResidue;		/**< AAL5 CRC Residue */} IxNpeA_TxAtmVc;/* Changes to field sizes or orders must be reflected in the offset * definitions above. *//** * @brief Rx Descriptor definition */typedef struct{    UINT32  rxBitField;			/**< Recieved bit field */    UINT32  atmCellHeader;		/**< ATM Cell Header */    UINT32  rsvdWord0;                  /**< Reserved field */    UINT16  currMbufLen;		/**< Mbuf Length */    UINT8   timeLimit; 			/**< Payload Reassembly timeLimit (used for aal0_xx only) */    UINT8   rsvdByte0;                  /**< Reserved field */     UINT32  rsvdWord1;   		/**< Reserved field */    IX_OSAL_MBUF *pCurrMbuf;		/**< Pointer to current mbuf */    unsigned char *pCurrMbufData;	/**< Pointer to current mbuf->data */    IX_OSAL_MBUF *pNextMbuf;		/**< Pointer to next mbuf */    UINT32  totalLen;			/**< Total Length */    UINT32  aal5CrcResidue;		/**< AAL5 CRC Residue */} IxNpeA_RxAtmVc;/** * @brief NPE-A AAL Type */typedef enum{    IX_NPE_A_AAL_TYPE_INVALID = 0,	/**< Invalid AAL type */    IX_NPE_A_AAL_TYPE_0_48    = 0x1,	/**< AAL0 - 48 byte */    IX_NPE_A_AAL_TYPE_0_52    = 0x2,	/**< AAL0 - 52 byte */    IX_NPE_A_AAL_TYPE_5       = 0x5,	/**< AAL5 */    IX_NPE_A_AAL_TYPE_OAM     = 0xF	/**< OAM */} IxNpeA_AalType;/** * @brief NPE-A Payload format 52-bytes & 48-bytes */typedef enum{    IX_NPE_A_52_BYTE_PAYLOAD = 0,	/**< 52 byte payload */    IX_NPE_A_48_BYTE_PAYLOAD		/**< 48 byte payload */} IxNpeA_PayloadFormat;/** * @brief  HSS Packetized NpePacket Descriptor Structure */typedef struct{    UINT8   status;		/**< Status of the packet passed to the client */    UINT8   errorCount;		/**< Number of errors */    UINT8   chainCount;		/**< Mbuf chain count e.g. 0 - No mbuf chain */    UINT8   rsvdByte0;		/**< Reserved byte to make the descriptor word align */    UINT16  packetLength;	/**< Packet Length */    UINT16  rsvdShort0;		/**< Reserved short to make the descriptor a word align */    IX_OSAL_MBUF *pRootMbuf;	/**< Pointer to Root mbuf */    IX_OSAL_MBUF *pNextMbuf;	/**< Pointer to next mbuf */    UINT8   *pMbufData;		/**< Pointer to the current mbuf->data */    UINT32  mbufLength;		/**< Current mbuf length */} IxNpeA_NpePacketDescriptor;#endif/** *@} */#endif /* __doxygen_HIDE */