/** * @file IxParityENAcc.h * * @author Intel Corporation * @date 24 Mar 2004 * * @brief This file contains the public API for the IXP400 Parity Error  * Notifier access component. * * @par * IXP400 SW Release version 2.0 *  * -- Copyright Notice -- *  * @par * Copyright 2001-2005, Intel Corporation. * All rights reserved. *  * @par * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * 1. Redistributions of source code must retain the above copyright *    notice, this list of conditions and the following disclaimer. * 2. Redistributions in binary form must reproduce the above copyright *    notice, this list of conditions and the following disclaimer in the *    documentation and/or other materials provided with the distribution. * 3. Neither the name of the Intel Corporation nor the names of its contributors *    may be used to endorse or promote products derived from this software *    without specific prior written permission. *  * @par * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS ``AS IS'' * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. *  * @par * -- End of Copyright Notice -- *//** * @defgroup IxParityENAcc IXP400 Parity Error Notifier (IxParityENAcc) API * * @brief The public API for the Parity Error Notifier  *  * @{ */#ifndef IXPARITYENACC_H#define IXPARITYENACC_H#ifdef __ixp46X#include "IxOsal.h"/* * #defines for function return types, etc. *//** * @ingroup IxParityENAcc * * @enum IxParityENAccStatus * * @brief The status as returend from the API */typedef enum /**< IxParityENAccStatus */{  IX_PARITYENACC_SUCCESS = IX_SUCCESS, /**< The request is successful */  IX_PARITYENACC_INVALID_PARAMETERS,   /**< Invalid or NULL parameters passed */  IX_PARITYENACC_NOT_INITIALISED,      /**< Access layer has not been initialised before accessing the APIs */  IX_PARITYENACC_ALREADY_INITIALISED,  /**< Access layer has already been initialised */   IX_PARITYENACC_OPERATION_FAILED,     /**< Operation did not succeed due to hardware failure */  IX_PARITYENACC_NO_PARITY             /**< No parity condition exits or has already been cleared */} IxParityENAccStatus;/** * @ingroup IxParityENAcc * * @enum IxParityENAccParityType *  * @brief Odd or Even Parity Type */typedef enum  /**< IxParityENAccParityType */{  IX_PARITYENACC_EVEN_PARITY,    /**< Even Parity */  IX_PARITYENACC_ODD_PARITY      /**< Odd Parity */} IxParityENAccParityType;/** * @ingroup IxParityENAcc * * @enum IxParityENAccConfigOption * * @brief The parity error enable/disable configuration option */typedef enum /**< IxParityENAccConfigOption */{  IX_PARITYENACC_DISABLE,       /**< Disable parity error detection */  IX_PARITYENACC_ENABLE         /**< Enable parity error detection */} IxParityENAccConfigOption;/** * @ingroup IxParityENAcc * * @struct IxParityENAccNpeConfig * * @brief NPE parity detection is to be enabled/disabled */typedef struct /**< IxParityENAccNpeConfig */{  IxParityENAccConfigOption ideEnabled; /**< NPE IMem, DMem and External */  IxParityENAccParityType parityOddEven; /**< Parity - Odd or Even */} IxParityENAccNpeConfig ;/** * @ingroup IxParityENAcc * * @struct IxParityENAccMcuConfig * * @brief MCU pairty detection is to be enabled/disabled */typedef struct /**< IxParityENAccMcuConfig */ {  IxParityENAccConfigOption singlebitDetectEnabled;      /**< Single-bit parity error detection */  IxParityENAccConfigOption singlebitCorrectionEnabled;  /**< Single-bit parity error correction */  IxParityENAccConfigOption multibitDetectionEnabled;    /**< Multi-bit  parity error detection */} IxParityENAccMcuConfig ;/** * @ingroup IxParityENAcc * * @struct IxParityENAccEbcConfig * * @brief Expansion Bus Controller parity detection is to be enabled or disabled  * * Note: All the Chip Select(s) and External Masters will have the same parity */typedef struct /**< IxParityENAccEbcConfig */{  IxParityENAccConfigOption ebcCs0Enabled;    /**< Expansion Bus Controller - Chip Select 0 */  IxParityENAccConfigOption ebcCs1Enabled;    /**< Expansion Bus Controller - Chip Select 1 */  IxParityENAccConfigOption ebcCs2Enabled;    /**< Expansion Bus Controller - Chip Select 2 */  IxParityENAccConfigOption ebcCs3Enabled;    /**< Expansion Bus Controller - Chip Select 3 */  IxParityENAccConfigOption ebcCs4Enabled;    /**< Expansion Bus Controller - Chip Select 4 */  IxParityENAccConfigOption ebcCs5Enabled;    /**< Expansion Bus Controller - Chip Select 5 */  IxParityENAccConfigOption ebcCs6Enabled;    /**< Expansion Bus Controller - Chip Select 6 */  IxParityENAccConfigOption ebcCs7Enabled;    /**< Expansion Bus Controller - Chip Select 7 */  IxParityENAccConfigOption ebcExtMstEnabled; /**< External Master on Expansion bus */  IxParityENAccParityType parityOddEven;      /**< Parity - Odd or Even */} IxParityENAccEbcConfig ;/** * @ingroup IxParityENAcc * * @struct IxParityENAccHWParityConfig * * @brief Parity error configuration of the Hardware Blocks */typedef struct /**< IxParityENAccHWParityConfig */{   IxParityENAccNpeConfig npeAConfig;     /**< NPE A parity detection is to be enabled/disabled */  IxParityENAccNpeConfig npeBConfig;     /**< NPE B parity detection is to be enabled/disabled */  IxParityENAccNpeConfig npeCConfig;     /**< NPE C parity detection is to be enabled/disabled */  IxParityENAccMcuConfig mcuConfig;      /**< MCU pairty detection is to be enabled/disabled */  IxParityENAccConfigOption swcpEnabled; /**< SWCP parity detection is to be enabled */  IxParityENAccConfigOption aqmEnabled;  /**< AQM parity detection is to be enabled */  IxParityENAccEbcConfig ebcConfig;      /**< Expansion Bus Controller parity detection is to be enabled/disabled */} IxParityENAccHWParityConfig;/** * @ingroup IxParityENAcc * * @struct IxParityENAccNpeParityErrorStats * * @brief NPE parity error statistics */typedef struct  /* IxParityENAccNpeParityErrorStats */{  UINT32 parityErrorsIMem;         /**< Parity errors in Instruction Memory */  UINT32 parityErrorsDMem;         /**< Parity errors in Data Memory */  UINT32 parityErrorsExternal;     /**< Parity errors in NPE External Entities */} IxParityENAccNpeParityErrorStats;/** * @ingroup IxParityENAcc * * @struct IxParityENAccMcuParityErrorStats * * @brief DDR Memory Control Unit parity error statistics *  * Note: There could be two outstanding parity errors at any given time whose address * details captured. If there is no room for the new interrupt then it would be treated * as overflow parity condition. */typedef struct  /* IxParityENAccMcuParityErrorStats */{  UINT32 parityErrorsSingleBit;    /**< Parity errors of the type Single-Bit */  UINT32 parityErrorsMultiBit;     /**< Parity errors of the type Multi-Bit */  UINT32 parityErrorsOverflow;     /**< Parity errors when more than two parity errors occured */} IxParityENAccMcuParityErrorStats;/** * @ingroup IxParityENAcc * * @struct IxParityENAccEbcParityErrorStats * * @brief Expansion Bus Controller parity error statistics */typedef struct  /* IxParityENAccEbcParityErrorStats */{  UINT32 parityErrorsInbound;      /**< Odd bit parity errors on inbound transfers */  UINT32 parityErrorsOutbound;     /**< Odd bit parity errors on outbound transfers */} IxParityENAccEbcParityErrorStats;/** * @ingroup IxParityENAcc * * @struct IxParityENAccParityErrorStats * * @brief Parity Error Statistics for the all the hardware blocks */typedef struct  /**< IxParityENAccParityErrorStats */{  IxParityENAccNpeParityErrorStats  npeStats;  /**< NPE parity error statistics */  IxParityENAccMcuParityErrorStats  mcuStats;  /**< MCU parity error statistics */  IxParityENAccEbcParityErrorStats  ebcStats;  /**< EBC parity error statistics */  UINT32                            swcpStats; /**< SWCP parity error statistics */  UINT32                            aqmStats;  /**< AQM parity error statistics */} IxParityENAccParityErrorStats;/** * @ingroup IxParityENAcc * * @enum IxParityENAccParityErrorSource * * @brief The source of the parity error notification  */typedef enum  /**< IxParityENAccParityErrorSource  */{  IX_PARITYENACC_NPE_A_IMEM,     /**< NPE A - Instruction memory */  IX_PARITYENACC_NPE_A_DMEM,     /**< NPE A - Data memory */  IX_PARITYENACC_NPE_A_EXT,      /**< NPE A - External Entity*/  IX_PARITYENACC_NPE_B_IMEM,     /**< NPE B - Instruction memory */  IX_PARITYENACC_NPE_B_DMEM,     /**< NPE B - Data memory */  IX_PARITYENACC_NPE_B_EXT,      /**< NPE B - External Entity*/  IX_PARITYENACC_NPE_C_IMEM,     /**< NPE C - Instruction memory */  IX_PARITYENACC_NPE_C_DMEM,     /**< NPE C - Data memory */  IX_PARITYENACC_NPE_C_EXT,      /**< NPE C - External Entity*/