/** * @def IX_NPEDL_ECS_DBG_CTXT_REG_0 * @brief Execution Access register address for register 0 at Debug *        Executing Context Stack level */#define IX_NPEDL_ECS_DBG_CTXT_REG_0          0x0C/** * @def IX_NPEDL_ECS_DBG_CTXT_REG_1 * @brief Execution Access register address for register 1 at Debug  *        Executing Context Stack level */#define IX_NPEDL_ECS_DBG_CTXT_REG_1          0x0D/** * @def IX_NPEDL_ECS_DBG_CTXT_REG_2 * @brief Execution Access register address for register 2 at Debug  *        Executing Context Stack level */#define IX_NPEDL_ECS_DBG_CTXT_REG_2          0x0E/** * @def IX_NPEDL_ECS_INSTRUCT_REG * @brief Execution Access register address for NPE Instruction Register  */#define IX_NPEDL_ECS_INSTRUCT_REG            0x11/* * Execution Access register reset values *//** * @def IX_NPEDL_ECS_BG_CTXT_REG_0_RESET * @brief Reset value for Execution Access Background ECS level register 0 */#define IX_NPEDL_ECS_BG_CTXT_REG_0_RESET     0xA0000000/** * @def IX_NPEDL_ECS_BG_CTXT_REG_1_RESET * @brief Reset value for Execution Access Background ECS level register 1 */#define IX_NPEDL_ECS_BG_CTXT_REG_1_RESET     0x01000000/** * @def IX_NPEDL_ECS_BG_CTXT_REG_2_RESET * @brief Reset value for Execution Access Background ECS level register 2 */#define IX_NPEDL_ECS_BG_CTXT_REG_2_RESET     0x00008000/** * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET * @brief Reset value for Execution Access Priority 1 ECS level register 0 */#define IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET  0x20000080/** * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET * @brief Reset value for Execution Access Priority 1 ECS level register 1 */#define IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET  0x01000000/** * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET * @brief Reset value for Execution Access Priority 1 ECS level register 2 */#define IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET  0x00008000/** * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET * @brief Reset value for Execution Access Priority 2 ECS level register 0 */#define IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET  0x20000080/** * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET * @brief Reset value for Execution Access Priority 2 ECS level register 1 */#define IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET  0x01000000/** * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET * @brief Reset value for Execution Access Priority 2 ECS level register 2 */#define IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET  0x00008000/** * @def IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET * @brief Reset value for Execution Access Debug ECS level register 0 */#define IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET    0x20000000/** * @def IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET * @brief Reset value for Execution Access Debug ECS level register 1 */#define IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET    0x00000000/** * @def IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET * @brief Reset value for Execution Access Debug ECS level register 2 */#define IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET    0x001E0000/** * @def IX_NPEDL_ECS_INSTRUCT_REG_RESET * @brief Reset value for Execution Access NPE Instruction Register */#define IX_NPEDL_ECS_INSTRUCT_REG_RESET      0x1003C00F/* * masks used to read/write particular bits in Execution Access registers *//** * @def IX_NPEDL_MASK_ECS_REG_0_ACTIVE * @brief Mask the A (Active) bit in Execution Access Register 0 of all ECS *        levels */#define IX_NPEDL_MASK_ECS_REG_0_ACTIVE       0x80000000/** * @def IX_NPEDL_MASK_ECS_REG_0_NEXTPC * @brief Mask the NextPC bits in Execution Access Register 0 of all ECS *        levels (except Debug ECS level) */#define IX_NPEDL_MASK_ECS_REG_0_NEXTPC       0x1FFF0000/** * @def IX_NPEDL_MASK_ECS_REG_0_LDUR * @brief Mask the LDUR bits in Execution Access Register 0 of all ECS levels */#define IX_NPEDL_MASK_ECS_REG_0_LDUR         0x00000700/** * @def IX_NPEDL_MASK_ECS_REG_1_CCTXT * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels */#define IX_NPEDL_MASK_ECS_REG_1_CCTXT        0x000F0000/** * @def IX_NPEDL_MASK_ECS_REG_1_SELCTXT * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels */#define IX_NPEDL_MASK_ECS_REG_1_SELCTXT      0x0000000F/** * @def IX_NPEDL_MASK_ECS_DBG_REG_2_IF * @brief Mask the IF bit in Execution Access Register 2 of Debug ECS level */#define IX_NPEDL_MASK_ECS_DBG_REG_2_IF       0x00100000/** * @def IX_NPEDL_MASK_ECS_DBG_REG_2_IE * @brief Mask the IE bit in Execution Access Register 2 of Debug ECS level */#define IX_NPEDL_MASK_ECS_DBG_REG_2_IE       0x00080000/* * Bit-Offsets from LSB of particular bit-fields in Execution Access registers *//** * @def IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC * @brief LSB-offset of NextPC field in Execution Access Register 0 of all ECS *        levels (except Debug ECS level) */#define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC     16 /** * @def IX_NPEDL_OFFSET_ECS_REG_0_LDUR * @brief LSB-offset of LDUR field in Execution Access Register 0 of all ECS *        levels */#define IX_NPEDL_OFFSET_ECS_REG_0_LDUR        8/** * @def IX_NPEDL_OFFSET_ECS_REG_1_CCTXT * @brief LSB-offset of CCTXT field in Execution Access Register 1 of all ECS *        levels */#define IX_NPEDL_OFFSET_ECS_REG_1_CCTXT      16/** * @def IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT * @brief LSB-offset of SELCTXT field in Execution Access Register 1 of all ECS *        levels */#define IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT     0/* * NPE core & co-processor instruction templates to load into NPE Instruction  * Register, for read/write of NPE register file registers *//** * @def IX_NPEDL_INSTR_RD_REG_BYTE * @brief NPE Instruction, used to read an 8-bit NPE internal logical register *        and return the value in the EXDATA register (aligned to MSB). *        NPE Assembler instruction:  "mov8 d0, d0  &&& DBG_WrExec" */#define IX_NPEDL_INSTR_RD_REG_BYTE    0x0FC00000/** * @def IX_NPEDL_INSTR_RD_REG_SHORT * @brief NPE Instruction, used to read a 16-bit NPE internal logical register *        and return the value in the EXDATA register (aligned to MSB). *        NPE Assembler instruction:  "mov16 d0, d0  &&& DBG_WrExec" */#define IX_NPEDL_INSTR_RD_REG_SHORT   0x0FC08010/** * @def IX_NPEDL_INSTR_RD_REG_WORD * @brief NPE Instruction, used to read a 16-bit NPE internal logical register *        and return the value in the EXDATA register. *        NPE Assembler instruction:  "mov32 d0, d0  &&& DBG_WrExec" */#define IX_NPEDL_INSTR_RD_REG_WORD    0x0FC08210/** * @def IX_NPEDL_INSTR_WR_REG_BYTE * @brief NPE Immediate-Mode Instruction, used to write an 8-bit NPE internal *        logical register. *        NPE Assembler instruction:  "mov8 d0, #0" */#define IX_NPEDL_INSTR_WR_REG_BYTE    0x00004000/** * @def IX_NPEDL_INSTR_WR_REG_SHORT * @brief NPE Immediate-Mode Instruction, used to write a 16-bit NPE internal *        logical register. *        NPE Assembler instruction:  "mov16 d0, #0" */#define IX_NPEDL_INSTR_WR_REG_SHORT   0x0000C000/** * @def IX_NPEDL_INSTR_RD_FIFO * @brief NPE Immediate-Mode Instruction, used to write a 16-bit NPE internal *        logical register. *        NPE Assembler instruction:  "cprd32 d0    &&& DBG_RdInFIFO" */#define IX_NPEDL_INSTR_RD_FIFO        0x0F888220    /** * @def IX_NPEDL_INSTR_RESET_MBOX * @brief NPE Instruction, used to reset Mailbox (MBST) register *        NPE Assembler instruction:  "mov32 d0, d0  &&& DBG_ClearM" */#define IX_NPEDL_INSTR_RESET_MBOX     0x0FAC8210/* * Bit-offsets from LSB, of particular bit-fields in an NPE instruction *//** * @def IX_NPEDL_OFFSET_INSTR_SRC * @brief LSB-offset to SRC (source operand) field of an NPE Instruction */#define IX_NPEDL_OFFSET_INSTR_SRC              4/** * @def IX_NPEDL_OFFSET_INSTR_DEST * @brief LSB-offset to DEST (destination operand) field of an NPE Instruction */#define IX_NPEDL_OFFSET_INSTR_DEST             9/** * @def IX_NPEDL_OFFSET_INSTR_COPROC * @brief LSB-offset to COPROC (coprocessor instruction) field of an NPE *        Instruction */#define IX_NPEDL_OFFSET_INSTR_COPROC          18/* * masks used to read/write particular bits of an NPE Instruction *//** * @def IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA * @brief Mask the bits of 16-bit data value (least-sig 5 bits) to be used in *        SRC field of immediate-mode NPE instruction */#define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA         0x1F /** * @def IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA * @brief Mask the bits of 16-bit data value (most-sig 11 bits) to be used in *        COPROC field of immediate-mode NPE instruction */#define IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA      0xFFE0/** * @def IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA * @brief LSB offset of the bit-field of 16-bit data value (most-sig 11 bits) *        to be used in COPROC field of immediate-mode NPE instruction */#define IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA    5/** * @def IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA * @brief Number of left-shifts required to align most-sig 11 bits of 16-bit *        data value into COPROC field of immediate-mode NPE instruction */#define IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA \     (IX_NPEDL_OFFSET_INSTR_COPROC - IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA)/** * @def IX_NPEDL_WR_INSTR_LDUR * @brief LDUR value used with immediate-mode NPE Instructions by the NpeDl *        for writing to NPE internal logical registers */#define IX_NPEDL_WR_INSTR_LDUR                     1/** * @def IX_NPEDL_RD_INSTR_LDUR * @brief LDUR value used with NON-immediate-mode NPE Instructions by the NpeDl *        for reading from NPE internal logical registers */#define IX_NPEDL_RD_INSTR_LDUR                     0/** * @enum IxNpeDlCtxtRegNum * @brief Numeric values to identify the NPE internal Context Store registers */typedef enum{    IX_NPEDL_CTXT_REG_STEVT = 0,  /**< identifies STEVT   */    IX_NPEDL_CTXT_REG_STARTPC,    /**< identifies STARTPC */    IX_NPEDL_CTXT_REG_REGMAP,     /**< identifies REGMAP  */    IX_NPEDL_CTXT_REG_CINDEX,     /**< identifies CINDEX  */    IX_NPEDL_CTXT_REG_MAX         /**< Total number of Context Store registers */} IxNpeDlCtxtRegNum;/* * NPE Context Store register logical addresses *//** * @def IX_NPEDL_CTXT_REG_ADDR_STEVT * @brief Logical address of STEVT NPE internal Context Store register */#define IX_NPEDL_CTXT_REG_ADDR_STEVT      0x0000001B/** * @def IX_NPEDL_CTXT_REG_ADDR_STARTPC * @brief Logical address of STARTPC NPE internal Context Store register */#define IX_NPEDL_CTXT_REG_ADDR_STARTPC    0x0000001C/** * @def IX_NPEDL_CTXT_REG_ADDR_REGMAP * @brief Logical address of REGMAP NPE internal Context Store register */#define IX_NPEDL_CTXT_REG_ADDR_REGMAP     0x0000001E/** * @def IX_NPEDL_CTXT_REG_ADDR_CINDEX * @brief Logical address of CINDEX NPE internal Context Store register */#define IX_NPEDL_CTXT_REG_ADDR_CINDEX     0x0000001F/* * NPE Context Store register reset values *//** * @def IX_NPEDL_CTXT_REG_RESET_STEVT * @brief Reset value of STEVT NPE internal Context Store register *        (STEVT = off, 0x80) */#define IX_NPEDL_CTXT_REG_RESET_STEVT     0x80/** * @def IX_NPEDL_CTXT_REG_RESET_STARTPC * @brief Reset value of STARTPC NPE internal Context Store register *        (STARTPC = 0x0000) */#define IX_NPEDL_CTXT_REG_RESET_STARTPC   0x0000/** * @def IX_NPEDL_CTXT_REG_RESET_REGMAP * @brief Reset value of REGMAP NPE internal Context Store register *        (REGMAP = d0->p0, d8->p2, d16->p4) */#define IX_NPEDL_CTXT_REG_RESET_REGMAP    0x0820/** * @def IX_NPEDL_CTXT_REG_RESET_CINDEX * @brief Reset value of CINDEX NPE internal Context Store register *        (CINDEX = 0) */#define IX_NPEDL_CTXT_REG_RESET_CINDEX    0x00/* * numeric range of context levels available on an NPE *//** * @def IX_NPEDL_CTXT_NUM_MIN * @brief Lowest NPE Context number in range */#define IX_NPEDL_CTXT_NUM_MIN             0/** * @def IX_NPEDL_CTXT_NUM_MAX * @brief Highest NPE Context number in range */#define IX_NPEDL_CTXT_NUM_MAX             15/* * Physical NPE internal registers *//** * @def IX_NPEDL_TOTAL_NUM_PHYS_REG * @brief Number of Physical registers currently supported *        Initial NPE implementations will have a 32-word register file. *        Later implementations may have a 64-word register file. */#define IX_NPEDL_TOTAL_NUM_PHYS_REG               32/** * @def IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP * @brief LSB-offset of Regmap number in Physical NPE register address, used *        for Physical To Logical register address mapping in the NPE */#define IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP      1/** * @def IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR * @brief Mask to extract a logical NPE register address from a physical *        register address, used for Physical To Logical address mapping */#define IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR   0x1#endif /* IXNPEDLNPEMGRECREGISTERS_P_H */