}    if (mode == NULL)    {	return (IX_ETH_ACC_FAIL);    }    REG_READ(ixEthAccMacBase[portId],	     IX_ETH_ACC_MAC_TX_CNTRL1,	     regval);    if( regval & IX_ETH_ACC_TX_CNTRL1_DUPLEX)    {	*mode = IX_ETH_ACC_HALF_DUPLEX;    }    else    {	*mode = IX_ETH_ACC_FULL_DUPLEX;    }    return IX_ETH_ACC_SUCCESS;}IxEthAccStatusixEthAccPortTxFrameAppendPaddingEnablePriv (IxEthAccPortId portId){    UINT32 regval;    /*Enable FCS computation by the MAC and appending to the      frame*/    IX_ETH_ACC_VALIDATE_PORT_ID(portId);    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))    {        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable Tx Frame Append Padding.\n",(INT32)portId,0,0,0,0,0);        return IX_ETH_ACC_SUCCESS ;    }    if (!IX_ETH_IS_PORT_INITIALIZED(portId))    {	return (IX_ETH_ACC_PORT_UNINITIALIZED);    }    REG_READ(ixEthAccMacBase[portId],	     IX_ETH_ACC_MAC_TX_CNTRL1,	     regval);    REG_WRITE(ixEthAccMacBase[portId],	      IX_ETH_ACC_MAC_TX_CNTRL1,	      regval |	      IX_ETH_ACC_TX_CNTRL1_PAD_EN);    ixEthAccMacState[portId].txPADAppend = TRUE;    return IX_ETH_ACC_SUCCESS;}IxEthAccStatusixEthAccPortTxFrameAppendPaddingDisablePriv (IxEthAccPortId portId){    UINT32 regval;    /*disable FCS computation and appending*/    /*Set bit 4 of Tx control register one to zero*/    IX_ETH_ACC_VALIDATE_PORT_ID(portId);    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))    {        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disble Tx Frame Append Padding.\n",(INT32)portId,0,0,0,0,0);        return IX_ETH_ACC_SUCCESS ;    }    if (!IX_ETH_IS_PORT_INITIALIZED(portId))    {	return (IX_ETH_ACC_PORT_UNINITIALIZED);    }    REG_READ(ixEthAccMacBase[portId],	     IX_ETH_ACC_MAC_TX_CNTRL1,	     regval);    REG_WRITE(ixEthAccMacBase[portId],	      IX_ETH_ACC_MAC_TX_CNTRL1,	      regval & ~IX_ETH_ACC_TX_CNTRL1_PAD_EN);    ixEthAccMacState[portId].txPADAppend = FALSE;    return IX_ETH_ACC_SUCCESS;}IxEthAccStatusixEthAccPortTxFrameAppendFCSEnablePriv (IxEthAccPortId portId){    UINT32 regval;    /*Enable FCS computation by the MAC and appending to the      frame*/    IX_ETH_ACC_VALIDATE_PORT_ID(portId);    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))    {        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable Tx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);        return IX_ETH_ACC_SUCCESS ;    }    if (!IX_ETH_IS_PORT_INITIALIZED(portId))    {	return (IX_ETH_ACC_PORT_UNINITIALIZED);    }    REG_READ(ixEthAccMacBase[portId],	     IX_ETH_ACC_MAC_TX_CNTRL1,	     regval);    REG_WRITE(ixEthAccMacBase[portId],	      IX_ETH_ACC_MAC_TX_CNTRL1,	      regval | IX_ETH_ACC_TX_CNTRL1_FCS_EN);    ixEthAccMacState[portId].txFCSAppend = TRUE;    return IX_ETH_ACC_SUCCESS;}IxEthAccStatusixEthAccPortTxFrameAppendFCSDisablePriv (IxEthAccPortId portId){    UINT32 regval;    /*disable FCS computation and appending*/    /*Set bit 4 of Tx control register one to zero*/    IX_ETH_ACC_VALIDATE_PORT_ID(portId);    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))    {        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable Tx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);        return IX_ETH_ACC_SUCCESS ;    }    if (!IX_ETH_IS_PORT_INITIALIZED(portId))    {	return (IX_ETH_ACC_PORT_UNINITIALIZED);    }    REG_READ(ixEthAccMacBase[portId],	     IX_ETH_ACC_MAC_TX_CNTRL1,	     regval);    REG_WRITE(ixEthAccMacBase[portId],	      IX_ETH_ACC_MAC_TX_CNTRL1,	      regval & ~IX_ETH_ACC_TX_CNTRL1_FCS_EN);    ixEthAccMacState[portId].txFCSAppend = FALSE;    return IX_ETH_ACC_SUCCESS;}IxEthAccStatusixEthAccPortRxFrameAppendFCSEnablePriv (IxEthAccPortId portId){    /*Set bit 2 of Rx control 1*/    UINT32 regval;    IX_ETH_ACC_VALIDATE_PORT_ID(portId);    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))    {        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot enable Rx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);        return IX_ETH_ACC_SUCCESS ;    }    if (!IX_ETH_IS_PORT_INITIALIZED(portId))    {	return (IX_ETH_ACC_PORT_UNINITIALIZED);    }    REG_READ(ixEthAccMacBase[portId],	     IX_ETH_ACC_MAC_RX_CNTRL1,	     regval);    REG_WRITE(ixEthAccMacBase[portId],	      IX_ETH_ACC_MAC_RX_CNTRL1,	      regval | IX_ETH_ACC_RX_CNTRL1_CRC_EN);    ixEthAccMacState[portId].rxFCSAppend = TRUE;    return IX_ETH_ACC_SUCCESS;}IxEthAccStatusixEthAccPortRxFrameAppendFCSDisablePriv (IxEthAccPortId portId){    UINT32 regval;    /*Clear bit 2 of Rx control 1*/    IX_ETH_ACC_VALIDATE_PORT_ID(portId);    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))    {        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot disable Rx Frame Append FCS.\n",(INT32)portId,0,0,0,0,0);        return IX_ETH_ACC_SUCCESS ;    }    if (!IX_ETH_IS_PORT_INITIALIZED(portId))    {	return (IX_ETH_ACC_PORT_UNINITIALIZED);    }    REG_READ(ixEthAccMacBase[portId],	     IX_ETH_ACC_MAC_RX_CNTRL1,	     regval);    REG_WRITE(ixEthAccMacBase[portId],	      IX_ETH_ACC_MAC_RX_CNTRL1,	      regval & ~IX_ETH_ACC_RX_CNTRL1_CRC_EN);    ixEthAccMacState[portId].rxFCSAppend = FALSE;    return IX_ETH_ACC_SUCCESS;}PRIVATE voidixEthAccMacNpeStatsMessageCallback (IxNpeMhNpeId npeId,				    IxNpeMhMessage msg){    IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);#ifndef NDEBUG    /* Prudent to at least check the port is within range */    if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)    {	IX_ETH_ACC_FATAL_LOG(     "IXETHACC:ixEthAccMacNpeStatsMessageCallback: Illegal port: %u\n",     (UINT32)portId, 0, 0, 0, 0, 0);	return;    }#endif    /*Unblock Stats Get call*/    ixOsalMutexUnlock(&ixEthAccMacState[portId].ackMIBStatsLock);}PRIVATE voidixEthAccMibIIStatsEndianConvert (IxEthEthObjStats *retStats){    /* endianness conversion */    /* Rx stats */    retStats->dot3StatsAlignmentErrors =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsAlignmentErrors);    retStats->dot3StatsFCSErrors =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsFCSErrors);    retStats->dot3StatsInternalMacReceiveErrors =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsInternalMacReceiveErrors);    retStats->RxOverrunDiscards =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxOverrunDiscards);    retStats->RxLearnedEntryDiscards =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxLearnedEntryDiscards);    retStats->RxLargeFramesDiscards =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxLargeFramesDiscards);    retStats->RxSTPBlockedDiscards =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxSTPBlockedDiscards);    retStats->RxVLANTypeFilterDiscards =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxVLANTypeFilterDiscards);    retStats->RxVLANIdFilterDiscards =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxVLANIdFilterDiscards);    retStats->RxInvalidSourceDiscards =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxInvalidSourceDiscards);    retStats->RxBlackListDiscards =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxBlackListDiscards);    retStats->RxWhiteListDiscards =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxWhiteListDiscards);    retStats->RxUnderflowEntryDiscards =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->RxUnderflowEntryDiscards);    /* Tx stats */    retStats->dot3StatsSingleCollisionFrames =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsSingleCollisionFrames);    retStats->dot3StatsMultipleCollisionFrames =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsMultipleCollisionFrames);    retStats->dot3StatsDeferredTransmissions =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsDeferredTransmissions);    retStats->dot3StatsLateCollisions =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsLateCollisions);    retStats->dot3StatsExcessiveCollsions =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsExcessiveCollsions);    retStats->dot3StatsInternalMacTransmitErrors =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsInternalMacTransmitErrors);    retStats->dot3StatsCarrierSenseErrors =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->dot3StatsCarrierSenseErrors);    retStats->TxLargeFrameDiscards =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->TxLargeFrameDiscards);    retStats->TxVLANIdFilterDiscards =	IX_OSAL_SWAP_BE_SHARED_LONG(retStats->TxVLANIdFilterDiscards);}IxEthAccStatusixEthAccMibIIStatsGet (IxEthAccPortId portId,		       IxEthEthObjStats *retStats ){    IxNpeMhMessage message;    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())    {        printf("EthAcc: ixEthAccMibIIStatsGet (Mac) EthAcc service is not initialized\n");	return (IX_ETH_ACC_FAIL);    }    IX_ETH_ACC_VALIDATE_PORT_ID(portId);    if (retStats == NULL)    {        printf("EthAcc: ixEthAccMibIIStatsGet (Mac) NULL argument\n");	return (IX_ETH_ACC_FAIL);    }    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))    {        printf("EthAcc: ixEthAccMibIIStatsGet (Mac) NPE for port %d is not available\n", portId);        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get MIB II Stats.\n",(INT32)portId,0,0,0,0,0);        /* Return all zero stats */        IX_ETH_ACC_MEMSET(retStats, 0, sizeof(IxEthEthObjStats));        return IX_ETH_ACC_SUCCESS ;    }    if (!IX_ETH_IS_PORT_INITIALIZED(portId))    {        printf("EthAcc: ixEthAccMibIIStatsGet (Mac) port %d is not initialized\n", portId);	return (IX_ETH_ACC_PORT_UNINITIALIZED);    }    IX_OSAL_CACHE_INVALIDATE(retStats, sizeof(IxEthEthObjStats));    message.data[0] = IX_ETHNPE_GETSTATS << IX_ETH_ACC_MAC_MSGID_SHL;    message.data[1] = (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS(retStats);    /* Permit only one task to request MIB statistics Get operation       at a time */    ixOsalMutexLock(&ixEthAccMacState[portId].MIBStatsGetAccessLock, IX_OSAL_WAIT_FOREVER);    if(ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),				      message,				      IX_ETHNPE_GETSTATS,				      ixEthAccMacNpeStatsMessageCallback,				      IX_NPEMH_SEND_RETRIES_DEFAULT)       != IX_SUCCESS)    {	ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetAccessLock);        printf("EthAcc: (Mac) StatsGet failed to send NPE message\n");	return IX_ETH_ACC_FAIL;    }    /* Wait for callback invocation indicating response to       this request - we need this mutex in order to ensure       that the return from this function is synchronous */    ixOsalMutexLock(&ixEthAccMacState[portId].ackMIBStatsLock, IX_ETH_ACC_MIB_STATS_DELAY_MSECS);    /* Permit other tasks to perform MIB statistics Get operation */    ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetAccessLock);    ixEthAccMibIIStatsEndianConvert (retStats);    return IX_ETH_ACC_SUCCESS;}PRIVATE voidixEthAccMacNpeStatsResetMessageCallback (IxNpeMhNpeId npeId,					 IxNpeMhMessage msg){    IxEthAccPortId portId = IX_ETH_ACC_NPE_TO_PORT_ID(npeId);#ifndef NDEBUG    /* Prudent to at least check the port is within range */    if (portId >= IX_ETH_ACC_NUMBER_OF_PORTS)    {	IX_ETH_ACC_FATAL_LOG(     "IXETHACC:ixEthAccMacNpeStatsResetMessageCallback: Illegal port: %u\n",     (UINT32)portId, 0, 0, 0, 0, 0);	return;    }#endif    /*Unblock Stats Get & reset call*/    ixOsalMutexUnlock(&ixEthAccMacState[portId].ackMIBStatsResetLock);}IxEthAccStatusixEthAccMibIIStatsGetClear (IxEthAccPortId portId,			    IxEthEthObjStats *retStats){    IxNpeMhMessage message;    if (!IX_ETH_ACC_IS_SERVICE_INITIALIZED())    {        printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) EthAcc service is not initialized\n");	return (IX_ETH_ACC_FAIL);    }    IX_ETH_ACC_VALIDATE_PORT_ID(portId);    if (retStats == NULL)    {        printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) NULL argument\n");	return (IX_ETH_ACC_FAIL);    }    if (IX_ETH_ACC_SUCCESS != ixEthAccSingleEthNpeCheck(portId))    {        printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) NPE for port %d is not available\n", portId);        IX_ETH_ACC_WARNING_LOG("EthAcc: Unavailable Eth %d: Cannot get and clear MIB II Stats.\n", (INT32)portId, 0, 0, 0, 0, 0);        /* Return all zero stats */        IX_ETH_ACC_MEMSET(retStats, 0, sizeof(IxEthEthObjStats));        return IX_ETH_ACC_SUCCESS ;    }    if (!IX_ETH_IS_PORT_INITIALIZED(portId))    {        printf("EthAcc: ixEthAccMibIIStatsGetClear (Mac) port %d is not initialized\n", portId);	return (IX_ETH_ACC_PORT_UNINITIALIZED);    }    IX_OSAL_CACHE_INVALIDATE(retStats, sizeof(IxEthEthObjStats));    message.data[0] = IX_ETHNPE_RESETSTATS << IX_ETH_ACC_MAC_MSGID_SHL;    message.data[1] = (UINT32) IX_OSAL_MMU_VIRT_TO_PHYS(retStats);    /* Permit only one task to request MIB statistics Get-Reset operation at a time */    ixOsalMutexLock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock, IX_OSAL_WAIT_FOREVER);    if(ixNpeMhMessageWithResponseSend(IX_ETH_ACC_PORT_TO_NPE_ID(portId),				      message,				      IX_ETHNPE_RESETSTATS,				      ixEthAccMacNpeStatsResetMessageCallback,				      IX_NPEMH_SEND_RETRIES_DEFAULT)       != IX_SUCCESS)    {	ixOsalMutexUnlock(&ixEthAccMacState[portId].MIBStatsGetResetAccessLock);        printf("EthAcc: (Mac) ixEthAccMibIIStatsGetClear failed to send NPE message\n");	return IX_ETH_ACC_FAIL;    }    /* Wait for callback invocation indicating response to this request */    ixOsalMutexLo