/* * (C) Copyright 2006 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * (C) Copyright 2006 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com * Alain Saurel,	    AMCC/IBM, alain.saurel@fr.ibm.com * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#include <common.h>#include <asm/processor.h>#include <ppc440.h>#include "sequoia.h"DECLARE_GLOBAL_DATA_PTR;extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/int board_early_init_f(void){	unsigned long sdr0_cust0;	unsigned long sdr0_pfc1, sdr0_pfc2;	register uint reg;	mtdcr(ebccfga, xbcfg);	mtdcr(ebccfgd, 0xb8400000);	/*--------------------------------------------------------------------	 * Setup the GPIO pins	 *-------------------------------------------------------------------*/	/* test-only: take GPIO init from pcs440ep ???? in config file */	out32(GPIO0_OR, 0x00000000);	out32(GPIO0_TCR, 0x0000000f);	out32(GPIO0_OSRL, 0x50015400);	out32(GPIO0_OSRH, 0x550050aa);	out32(GPIO0_TSRL, 0x50015400);	out32(GPIO0_TSRH, 0x55005000);	out32(GPIO0_ISR1L, 0x50000000);	out32(GPIO0_ISR1H, 0x00000000);	out32(GPIO0_ISR2L, 0x00000000);	out32(GPIO0_ISR2H, 0x00000100);	out32(GPIO0_ISR3L, 0x00000000);	out32(GPIO0_ISR3H, 0x00000000);	out32(GPIO1_OR, 0x00000000);	out32(GPIO1_TCR, 0xc2000000);	out32(GPIO1_OSRL, 0x5c280000);	out32(GPIO1_OSRH, 0x00000000);	out32(GPIO1_TSRL, 0x0c000000);	out32(GPIO1_TSRH, 0x00000000);	out32(GPIO1_ISR1L, 0x00005550);	out32(GPIO1_ISR1H, 0x00000000);	out32(GPIO1_ISR2L, 0x00050000);	out32(GPIO1_ISR2H, 0x00000000);	out32(GPIO1_ISR3L, 0x01400000);	out32(GPIO1_ISR3H, 0x00000000);	/*--------------------------------------------------------------------	 * Setup the interrupt controller polarities, triggers, etc.	 *-------------------------------------------------------------------*/	mtdcr(uic0sr, 0xffffffff);	/* clear all */	mtdcr(uic0er, 0x00000000);	/* disable all */	mtdcr(uic0cr, 0x00000005);	/* ATI & UIC1 crit are critical */	mtdcr(uic0pr, 0xfffff7ff);	/* per ref-board manual */	mtdcr(uic0tr, 0x00000000);	/* per ref-board manual */	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */	mtdcr(uic0sr, 0xffffffff);	/* clear all */	mtdcr(uic1sr, 0xffffffff);	/* clear all */	mtdcr(uic1er, 0x00000000);	/* disable all */	mtdcr(uic1cr, 0x00000000);	/* all non-critical */	mtdcr(uic1pr, 0xffffffff);	/* per ref-board manual */	mtdcr(uic1tr, 0x00000000);	/* per ref-board manual */	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */	mtdcr(uic1sr, 0xffffffff);	/* clear all */	mtdcr(uic2sr, 0xffffffff);	/* clear all */	mtdcr(uic2er, 0x00000000);	/* disable all */	mtdcr(uic2cr, 0x00000000);	/* all non-critical */	mtdcr(uic2pr, 0xffffffff);	/* per ref-board manual */	mtdcr(uic2tr, 0x00000000);	/* per ref-board manual */	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */	mtdcr(uic2sr, 0xffffffff);	/* clear all */	/* 50MHz tmrclk */	*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;	/* clear write protects */	*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;	/* enable Ethernet */	*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0x00;	/* enable USB device */	*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x20;	/* select Ethernet pins */	mfsdr(SDR0_PFC1, sdr0_pfc1);	sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) | SDR0_PFC1_SELECT_CONFIG_4;	mfsdr(SDR0_PFC2, sdr0_pfc2);	sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) | SDR0_PFC2_SELECT_CONFIG_4;	mtsdr(SDR0_PFC2, sdr0_pfc2);	mtsdr(SDR0_PFC1, sdr0_pfc1);	/* PCI arbiter enabled */	mfsdr(sdr_pci0, reg);	mtsdr(sdr_pci0, 0x80000000 | reg);	/* setup NAND FLASH */	mfsdr(SDR0_CUST0, sdr0_cust0);	sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL	|		SDR0_CUST0_NDFC_ENABLE		|		SDR0_CUST0_NDFC_BW_8_BIT	|		SDR0_CUST0_NDFC_ARE_MASK	|		(0x80000000 >> (28 + CFG_NAND_CS));	mtsdr(SDR0_CUST0, sdr0_cust0);	return 0;}/*---------------------------------------------------------------------------+  | misc_init_r.  +---------------------------------------------------------------------------*/int misc_init_r(void){	uint pbcr;	int size_val = 0;#ifdef CONFIG_440EPX	unsigned long usb2d0cr = 0;	unsigned long usb2phy0cr, usb2h0cr = 0;	unsigned long sdr0_pfc1;	char *act = getenv("usbact");#endif	/*	 * FLASH stuff...	 */	/* Re-do sizing to get full correct info */#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)	mtdcr(ebccfga, pb3cr);#else	mtdcr(ebccfga, pb0cr);#endif	pbcr = mfdcr(ebccfgd);	switch (gd->bd->bi_flashsize) {	case 1 << 20:		size_val = 0;		break;	case 2 << 20:		size_val = 1;		break;	case 4 << 20:		size_val = 2;		break;	case 8 << 20:		size_val = 3;		break;	case 16 << 20:		size_val = 4;		break;	case 32 << 20:		size_val = 5;		break;	case 64 << 20:		size_val = 6;		break;	case 128 << 20:		size_val = 7;		break;	}	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)	mtdcr(ebccfga, pb3cr);#else	mtdcr(ebccfga, pb0cr);#endif	mtdcr(ebccfgd, pbcr);	/* adjust flash start and offset */	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;	gd->bd->bi_flashoffset = 0;#ifdef CFG_ENV_IS_IN_FLASH	/* Monitor protection ON by default */	(void)flash_protect(FLAG_PROTECT_SET,			    -CFG_MONITOR_LEN,			    0xffffffff,			    &flash_info[0]);	/* Env protection ON by default */	(void)flash_protect(FLAG_PROTECT_SET,			    CFG_ENV_ADDR_REDUND,			    CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,			    &flash_info[0]);#endif	/*	 * USB suff...	 */#ifdef CONFIG_440EPX	if (act == NULL || strcmp(act, "hostdev") == 0)	{		/* SDR Setting */		mfsdr(SDR0_PFC1, sdr0_pfc1);		mfsdr(SDR0_USB0, usb2d0cr);		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);		mfsdr(SDR0_USB2H0CR, usb2h0cr);		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;	/*1*/		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/		/* An 8-bit/60MHz interface is the only possible alternative		   when connecting the Device to the PHY */		usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;		usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;	/*1*/		/* To enable the USB 2.0 Device function through the UTMI interface */		usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;		usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;		/*1*/		sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;		sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;		/*0*/		mtsdr(SDR0_PFC1, sdr0_pfc1);		mtsdr(SDR0_USB0, usb2d0cr);		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);		mtsdr(SDR0_USB2H0CR, usb2h0cr);		/*clear resets*/		udelay (1000);		mtsdr(SDR0_SRST1, 0x00000000);		udelay (1000);		mtsdr(SDR0_SRST0, 0x00000000);		printf("USB:   Host(int phy) Device(ext phy)\n");	} else if (strcmp(act, "dev") == 0) {		/*-------------------PATCH-------------------------------*/		mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;	/*0*/		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;		/*0*/		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;		/*1*/		usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;		usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;		/*1*/		mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);		udelay (1000);		mtsdr(SDR0_SRST1, 0x672c6000);		udelay (1000);		mtsdr(SDR0_SRST0, 0x00000080);		udelay (1000);		mtsdr(SDR0_SRST1, 0x60206000);