/* *  Copyright (C) 2004 PaulReynolds@lhsolutions.com * * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#include <common.h>#include "ocotea.h"#include <asm/processor.h>#include <spd_sdram.h>#include <ppc4xx_enet.h>DECLARE_GLOBAL_DATA_PTR;#define BOOT_SMALL_FLASH	32	/* 00100000 */#define FLASH_ONBD_N		2	/* 00000010 */#define FLASH_SRAM_SEL		1	/* 00000001 */long int fixed_sdram (void);void fpga_init (void);int board_early_init_f (void){	unsigned long mfr;	unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;	unsigned char switch_status;	unsigned long cs0_base;	unsigned long cs0_size;	unsigned long cs0_twt;	unsigned long cs2_base;	unsigned long cs2_size;	unsigned long cs2_twt;	/*-------------------------------------------------------------------------+	  | Initialize EBC CONFIG	  +-------------------------------------------------------------------------*/	mtebc(xbcfg, EBC_CFG_LE_UNLOCK |	      EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |	      EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |	      EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |	      EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);	/*-------------------------------------------------------------------------+	  | FPGA. Initialize bank 7 with default values.	  +-------------------------------------------------------------------------*/	mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|	      EBC_BXAP_BCE_DISABLE|	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|	      EBC_BXAP_BEM_WRITEONLY|	      EBC_BXAP_PEN_DISABLED);	mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);	/* read FPGA base register FPGA_REG0 */	switch_status = *fpga_base;	if (switch_status & 0x40) {		cs0_base = 0xFFE00000;		cs0_size = EBC_BXCR_BS_2MB;		cs0_twt = 8;		cs2_base = 0xFF800000;		cs2_size = EBC_BXCR_BS_4MB;		cs2_twt = 10;	} else {		cs0_base = 0xFFC00000;		cs0_size = EBC_BXCR_BS_4MB;		cs0_twt = 10;		cs2_base = 0xFF800000;		cs2_size = EBC_BXCR_BS_2MB;		cs2_twt = 8;	}	/*-------------------------------------------------------------------------+	  | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.	  +-------------------------------------------------------------------------*/	mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|	      EBC_BXAP_BCE_DISABLE|	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|	      EBC_BXAP_BEM_WRITEONLY|	      EBC_BXAP_PEN_DISABLED);	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(cs0_base)|	      cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);	/*-------------------------------------------------------------------------+	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.	  +-------------------------------------------------------------------------*/	mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|	      EBC_BXAP_BCE_DISABLE|	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|	      EBC_BXAP_BEM_WRITEONLY|	      EBC_BXAP_PEN_DISABLED);	mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x48000000)|	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);	/*-------------------------------------------------------------------------+	  | 4 MB FLASH. Initialize bank 2 with default values.	  +-------------------------------------------------------------------------*/	mtebc(pb2ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|	      EBC_BXAP_BCE_DISABLE|	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|	      EBC_BXAP_BEM_WRITEONLY|	      EBC_BXAP_PEN_DISABLED);	mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(cs2_base)|	      cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);	/*-------------------------------------------------------------------------+	  | FPGA. Initialize bank 7 with default values.	  +-------------------------------------------------------------------------*/	mtebc(pb7ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|	      EBC_BXAP_BCE_DISABLE|	      EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|	      EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|	      EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|	      EBC_BXAP_BEM_WRITEONLY|	      EBC_BXAP_PEN_DISABLED);	mtebc(pb7cr, EBC_BXCR_BAS_ENCODE(0x48300000)|	      EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);	/*--------------------------------------------------------------------	 * Setup the interrupt controller polarities, triggers, etc.	 *-------------------------------------------------------------------*/	mtdcr (uic0sr, 0xffffffff);	/* clear all */	mtdcr (uic0er, 0x00000000);	/* disable all */	mtdcr (uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */	mtdcr (uic0pr, 0xfffffe13);	/* per ref-board manual */	mtdcr (uic0tr, 0x01c00008);	/* per ref-board manual */	mtdcr (uic0vr, 0x00000001);	/* int31 highest, base=0x000 */	mtdcr (uic0sr, 0xffffffff);	/* clear all */	mtdcr (uic1sr, 0xffffffff);	/* clear all */	mtdcr (uic1er, 0x00000000);	/* disable all */	mtdcr (uic1cr, 0x00000000);	/* all non-critical */	mtdcr (uic1pr, 0xffffe0ff);	/* per ref-board manual */	mtdcr (uic1tr, 0x00ffc000);	/* per ref-board manual */	mtdcr (uic1vr, 0x00000001);	/* int31 highest, base=0x000 */	mtdcr (uic1sr, 0xffffffff);	/* clear all */	mtdcr (uic2sr, 0xffffffff);	/* clear all */	mtdcr (uic2er, 0x00000000);	/* disable all */	mtdcr (uic2cr, 0x00000000);	/* all non-critical */	mtdcr (uic2pr, 0xffffffff);	/* per ref-board manual */	mtdcr (uic2tr, 0x00ff8c0f);	/* per ref-board manual */	mtdcr (uic2vr, 0x00000001);	/* int31 highest, base=0x000 */	mtdcr (uic2sr, 0xffffffff);	/* clear all */	mtdcr (uicb0sr, 0xfc000000); /* clear all */	mtdcr (uicb0er, 0x00000000); /* disable all */	mtdcr (uicb0cr, 0x00000000); /* all non-critical */	mtdcr (uicb0pr, 0xfc000000); /* */	mtdcr (uicb0tr, 0x00000000); /* */	mtdcr (uicb0vr, 0x00000001); /* */	mfsdr (sdr_mfr, mfr);	mfr &= ~SDR0_MFR_ECS_MASK;/*	mtsdr(sdr_mfr, mfr); */	fpga_init();	return 0;}int checkboard (void){	char *s = getenv ("serial#");	printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");	if (s != NULL) {		puts (", serial# ");		puts (s);	}	putc ('\n');	return (0);}long int initdram (int board_type){	long dram_size = 0;#if defined(CONFIG_SPD_EEPROM)	dram_size = spd_sdram ();#else	dram_size = fixed_sdram ();#endif	return dram_size;}#if defined(CFG_DRAM_TEST)int testdram (void){	uint *pstart = (uint *) 0x00000000;	uint *pend = (uint *) 0x08000000;	uint *p;	for (p = pstart; p < pend; p++)		*p = 0xaaaaaaaa;	for (p = pstart; p < pend; p++) {		if (*p != 0xaaaaaaaa) {			printf ("SDRAM test fails at: %08x\n", (uint) p);			return 1;		}	}	for (p = pstart; p < pend; p++)		*p = 0x55555555;	for (p = pstart; p < pend; p++) {		if (*p != 0x55555555) {			printf ("SDRAM test fails at: %08x\n", (uint) p);			return 1;		}	}	return 0;}#endif#if !defined(CONFIG_SPD_EEPROM)/************************************************************************* *  fixed sdram init -- doesn't use serial presence detect. * *  Assumes:    128 MB, non-ECC, non-registered *              PLB @ 133 MHz * ************************************************************************/long int fixed_sdram (void){	uint reg;	/*--------------------------------------------------------------------	 * Setup some default	 *------------------------------------------------------------------*/	mtsdram (mem_uabba, 0x00000000);	/* ubba=0 (default)             */	mtsdram (mem_slio, 0x00000000);		/* rdre=0 wrre=0 rarw=0         */	mtsdram (mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)          */	mtsdram (mem_wddctr, 0x00000000);	/* wrcp=0 dcd=0                 */