/* * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */#include <common.h>#include <ppc4xx.h>#include <asm/processor.h>#include <spd_sdram.h>DECLARE_GLOBAL_DATA_PTR;extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/int board_early_init_f(void){	register uint reg;	/*--------------------------------------------------------------------	 * Setup the external bus controller/chip selects	 *-------------------------------------------------------------------*/	mtdcr(ebccfga, xbcfg);	reg = mfdcr(ebccfgd);	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */	mtebc(pb0ap, 0x03017300);	/* FLASH/SRAM */	mtebc(pb0cr, 0xfc0da000);	/* BAS=0xfc0 64MB r/w 16-bit */	mtebc(pb1ap, 0x00000000);	mtebc(pb1cr, 0x00000000);	mtebc(pb2ap, 0x04814500);	/*CPLD*/ mtebc(pb2cr, 0x80018000);	/*BAS=0x800 1MB r/w 8-bit */	mtebc(pb3ap, 0x00000000);	mtebc(pb3cr, 0x00000000);	mtebc(pb4ap, 0x00000000);	mtebc(pb4cr, 0x00000000);	mtebc(pb5ap, 0x00000000);	mtebc(pb5cr, 0x00000000);	/*--------------------------------------------------------------------	 * Setup the GPIO pins	 *-------------------------------------------------------------------*/	/*CPLD cs */	/*setup Address lines for flash size 64Meg. */	out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x50010000);	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x50010000);	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x50000000);	/*setup emac */	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);	out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);	out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);	out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);	/*UART1 */	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);	out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);	/* external interrupts IRQ0...3 */	out32(GPIO1_TCR, in32(GPIO1_TCR) & ~0x00f00000);	out32(GPIO1_TSRL, in32(GPIO1_TSRL) & ~0x0000ff00);	out32(GPIO1_ISR1L, in32(GPIO1_ISR1L) | 0x00005500);	/*setup USB 2.0 */	out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);	out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);	out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);	out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);	out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);	/*--------------------------------------------------------------------	 * Setup the interrupt controller polarities, triggers, etc.	 *-------------------------------------------------------------------*/	mtdcr(uic0sr, 0xffffffff);	/* clear all */	mtdcr(uic0er, 0x00000000);	/* disable all */	mtdcr(uic0cr, 0x00000009);	/* ATI & UIC1 crit are critical */	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */	mtdcr(uic0sr, 0xffffffff);	/* clear all */	mtdcr(uic1sr, 0xffffffff);	/* clear all */	mtdcr(uic1er, 0x00000000);	/* disable all */	mtdcr(uic1cr, 0x00000000);	/* all non-critical */	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */	mtdcr(uic1sr, 0xffffffff);	/* clear all */	/*--------------------------------------------------------------------	 * Setup other serial configuration	 *-------------------------------------------------------------------*/	mfsdr(sdr_pci0, reg);	mtsdr(sdr_pci0, 0x80000000 | reg);	/* PCI arbiter enabled */	mtsdr(sdr_pfc0, 0x00003e00);	/* Pin function */	mtsdr(sdr_pfc1, 0x00048000);	/* Pin function: UART0 has 4 pins */	/*clear tmrclk divisor */	*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;	/*enable ethernet */	*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;	/*enable usb 1.1 fs device and remove usb 2.0 reset */	*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;	/*get rid of flash write protect */	*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;	return 0;}int misc_init_r (void){	uint pbcr;	int size_val = 0;	/* Re-do sizing to get full correct info */	mtdcr(ebccfga, pb0cr);	pbcr = mfdcr(ebccfgd);	switch (gd->bd->bi_flashsize) {	case 1 << 20:		size_val = 0;		break;	case 2 << 20:		size_val = 1;		break;	case 4 << 20:		size_val = 2;		break;	case 8 << 20:		size_val = 3;		break;	case 16 << 20:		size_val = 4;		break;	case 32 << 20:		size_val = 5;		break;	case 64 << 20:		size_val = 6;		break;	case 128 << 20:		size_val = 7;		break;	}	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);	mtdcr(ebccfga, pb0cr);	mtdcr(ebccfgd, pbcr);	/* adjust flash start and offset */	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;	gd->bd->bi_flashoffset = 0;	/* Monitor protection ON by default */	(void)flash_protect(FLAG_PROTECT_SET,			    -CFG_MONITOR_LEN,			    0xffffffff,			    &flash_info[0]);	return 0;}int checkboard(void){	char *s = getenv("serial#");	printf("Board: Yosemite - AMCC PPC440EP Evaluation Board");	if (s != NULL) {		puts(", serial# ");		puts(s);	}	putc('\n');	return (0);}/************************************************************************* *  sdram_init -- doesn't use serial presence detect. * *  Assumes:    256 MB, ECC, non-registered *              PLB @ 133 MHz * ************************************************************************/#define NUM_TRIES 64#define NUM_READS 10void sdram_tr1_set(int ram_address, int* tr1_value){	int i;	int j, k;	volatile unsigned int* ram_pointer =  (unsigned int*)ram_address;	int first_good = -1, last_bad = 0x1ff;	unsigned long test[NUM_TRIES] = {		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,		0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,		0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,		0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,		0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,		0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,		0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,		0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,		0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55 };	/* go through all possible SDRAM0_TR1[RDCT] values */	for (i=0; i<=0x1ff; i++) {		/* set the current value for TR1 */		mtsdram(mem_tr1, (0x80800800 | i));		/* write values */		for (j=0; j<NUM_TRIES; j++) {			ram_pointer[j] = test[j];			/* clear any cache at ram location */			__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));		}		/* read values back */		for (j=0; j<NUM_TRIES; j++) {			for (k=0; k<NUM_READS; k++) {				/* clear any cache at ram location */				__asm__("dcbf 0,%0": :"r" (&ram_pointer[j]));				if (ram_pointer[j] != test[j])					break;			}			/* read error */			if (k != NUM_READS) {				break;			}		}		/* we have a SDRAM0_TR1[RDCT] that is part of the window */		if (j == NUM_TRIES) {			if (first_good == -1)				first_good = i;		/* found beginning of window */		} else { /* bad read */			/* if we have not had a good read then don't care */			if(first_good != -1) {				/* first failure after a good read */				last_bad = i-1;				break;			}		}	}