/* return the current value for TR1 */	*tr1_value = (first_good + last_bad) / 2;}void sdram_init(void){	register uint reg;	int tr1_bank1, tr1_bank2;	/*--------------------------------------------------------------------	 * Setup some default	 *------------------------------------------------------------------*/	mtsdram(mem_uabba, 0x00000000);	/* ubba=0 (default)             */	mtsdram(mem_slio, 0x00000000);	/* rdre=0 wrre=0 rarw=0         */	mtsdram(mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)          */	mtsdram(mem_clktr, 0x40000000);	/* ?? */	mtsdram(mem_wddctr, 0x40000000);	/* ?? */	/*clear this first, if the DDR is enabled by a debugger	  then you can not make changes. */	mtsdram(mem_cfg0, 0x00000000);	/* Disable EEC */	/*--------------------------------------------------------------------	 * Setup for board-specific specific mem	 *------------------------------------------------------------------*/	/*	 * Following for CAS Latency = 2.5 @ 133 MHz PLB	 */	mtsdram(mem_b0cr, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */	mtsdram(mem_b1cr, 0x080a4001);	/* SDBA=0x080 128MB, Mode 3, enabled */	mtsdram(mem_tr0, 0x410a4012);	/* ?? */	mtsdram(mem_rtr, 0x04080000);	/* ?? */	mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM    */	mtsdram(mem_cfg0, 0x30000000);	/* Disable EEC */	udelay(400);		/* Delay 200 usecs (min)            */	/*--------------------------------------------------------------------	 * Enable the controller, then wait for DCEN to complete	 *------------------------------------------------------------------*/	mtsdram(mem_cfg0, 0x80000000);	/* Enable */	for (;;) {		mfsdram(mem_mcsts, reg);		if (reg & 0x80000000)			break;	}	sdram_tr1_set(0x00000000, &tr1_bank1);	sdram_tr1_set(0x08000000, &tr1_bank2);	mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800) );}/************************************************************************* *  long int initdram * ************************************************************************/long int initdram(int board){	sdram_init();	return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);	/* return bytes */}#if defined(CFG_DRAM_TEST)int testdram(void){	unsigned long *mem = (unsigned long *)0;	const unsigned long kend = (1024 / sizeof(unsigned long));	unsigned long k, n;	mtmsr(0);	for (k = 0; k < CFG_KBYTES_SDRAM;	     ++k, mem += (1024 / sizeof(unsigned long))) {		if ((k & 1023) == 0) {			printf("%3d MB\r", k / 1024);		}		memset(mem, 0xaaaaaaaa, 1024);		for (n = 0; n < kend; ++n) {			if (mem[n] != 0xaaaaaaaa) {				printf("SDRAM test fails at: %08x\n",				       (uint) & mem[n]);				return 1;			}		}		memset(mem, 0x55555555, 1024);		for (n = 0; n < kend; ++n) {			if (mem[n] != 0x55555555) {				printf("SDRAM test fails at: %08x\n",				       (uint) & mem[n]);				return 1;			}		}	}	printf("SDRAM test passes\n");	return 0;}#endif/************************************************************************* *  pci_pre_init * *  This routine is called just prior to registering the hose and gives *  the board the opportunity to check things. Returning a value of zero *  indicates that things are bad & PCI initialization should be aborted. * *	Different boards may wish to customize the pci controller structure *	(add regions, override default access routines, etc) or perform *	certain pre-initialization actions. * ************************************************************************/#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)int pci_pre_init(struct pci_controller *hose){	unsigned long addr;	/*-------------------------------------------------------------------------+	  | Set priority for all PLB3 devices to 0.	  | Set PLB3 arbiter to fair mode.	  +-------------------------------------------------------------------------*/	mfsdr(sdr_amp1, addr);	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);	addr = mfdcr(plb3_acr);	mtdcr(plb3_acr, addr | 0x80000000);	/*-------------------------------------------------------------------------+	  | Set priority for all PLB4 devices to 0.	  +-------------------------------------------------------------------------*/	mfsdr(sdr_amp0, addr);	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */	mtdcr(plb4_acr, addr);	/*-------------------------------------------------------------------------+	  | Set Nebula PLB4 arbiter to fair mode.	  +-------------------------------------------------------------------------*/	/* Segment0 */	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;	addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;	addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;	mtdcr(plb0_acr, addr);	/* Segment1 */	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;	addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;	addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;	mtdcr(plb1_acr, addr);	return 1;}#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) *//************************************************************************* *  pci_target_init * *	The bootstrap configuration provides default settings for the pci *	inbound map (PIM). But the bootstrap config choices are limited and *	may not be sufficient for a given board. * ************************************************************************/#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)void pci_target_init(struct pci_controller *hose){	/*--------------------------------------------------------------------------+	 * Set up Direct MMIO registers	 *--------------------------------------------------------------------------*/	/*--------------------------------------------------------------------------+	  | PowerPC440 EP PCI Master configuration.	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF	  |   Use byte reversed out routines to handle endianess.	  | Make this region non-prefetchable.	  +--------------------------------------------------------------------------*/	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */	/*--------------------------------------------------------------------------+	 * Set up Configuration registers	 *--------------------------------------------------------------------------*/	/* Program the board's subsystem id/vendor id */	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,			      CFG_PCI_SUBSYS_VENDORID);	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);	/* Configure command register as bus master */	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);	/* 240nS PCI clock */	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);	/* No error reporting */	pci_write_config_word(0, PCI_ERREN, 0);	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);}#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) *//************************************************************************* *  pci_master_init * ************************************************************************/#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)void pci_master_init(struct pci_controller *hose){	unsigned short temp_short;	/*--------------------------------------------------------------------------+	  | Write the PowerPC440 EP PCI Configuration regs.	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).	  +--------------------------------------------------------------------------*/	pci_read_config_word(0, PCI_COMMAND, &temp_short);	pci_write_config_word(0, PCI_COMMAND,			      temp_short | PCI_COMMAND_MASTER |			      PCI_COMMAND_MEMORY);}#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) *//************************************************************************* *  is_pci_host * *	This routine is called to determine if a pci scan should be *	performed. With various hardware environments (especially cPCI and *	PPMC) it's insufficient to depend on the state of the arbiter enable *	bit in the strap register, or generic host/adapter assumptions. * *	Rather than hard-code a bad assumption in the general 440 code, the *	440 pci code requires the board to decide at runtime. * *	Return 0 for adapter mode, non-zero for host (monarch) mode. * * ************************************************************************/#if defined(CONFIG_PCI)int is_pci_host(struct pci_controller *hose){	/* Bamboo is always configured as host. */	return (1);}#endif				/* defined(CONFIG_PCI) *//************************************************************************* *  hw_watchdog_reset * *	This routine is called to reset (keep alive) the watchdog timer * ************************************************************************/#if defined(CONFIG_HW_WATCHDOG)void hw_watchdog_reset(void){}#endif