* * Fixed memory is composed of : *	MT46V16M16TG-75 from Micron (x 2), 256Mb, 16 M x16, DDR266, *	13 row add bits, 10 column add bits (but 12 row used only). *	ECC device: MT46V16M8TG-75 from Micron (x 1), 128Mb, x8, DDR266, *	12 row add bits, 10 column add bits. *	Prepare a subset (only the used ones) of SPD data * *	Note : if the ECC is enabled (SDRAM_ECC_ENABLE) the size of *	the corresponding bank is divided by 2 due to number of Row addresses *	12 in the ECC module * *  Assumes:	64 MB, ECC, non-registered *		PLB @ 133 MHz * ************************************************************************/static void init_spd_array(void){	cfg_simulate_spd_eeprom[8]     = 0x04;    /* 2.5 Volt */	cfg_simulate_spd_eeprom[2]     = 0x07;    /* DDR ram */#ifdef CONFIG_DDR_ECC	cfg_simulate_spd_eeprom[11]    = 0x02;    /* ECC ON : 02 OFF : 00 */	cfg_simulate_spd_eeprom[31]    = 0x08;    /* bankSizeID: 32MB */	cfg_simulate_spd_eeprom[3]     = 0x0C;    /* num Row Addr: 12 */#else	cfg_simulate_spd_eeprom[11]    = 0x00;    /* ECC ON : 02 OFF : 00 */	cfg_simulate_spd_eeprom[31]    = 0x10;    /* bankSizeID: 64MB */	cfg_simulate_spd_eeprom[3]     = 0x0D;    /* num Row Addr: 13 */#endif	cfg_simulate_spd_eeprom[4]     = 0x09;    /* numColAddr: 9  */	cfg_simulate_spd_eeprom[5]     = 0x01;    /* numBanks: 1 */	cfg_simulate_spd_eeprom[0]     = 0x80;    /* number of SPD bytes used: 128 */	cfg_simulate_spd_eeprom[1]     = 0x08;    /*  total number bytes in SPD device = 256 */	cfg_simulate_spd_eeprom[21]    = 0x00;    /* not registered: 0  registered : 0x02*/	cfg_simulate_spd_eeprom[6]     = 0x20;    /* Module data width: 32 bits */	cfg_simulate_spd_eeprom[7]     = 0x00;    /* Module data width continued: +0 */	cfg_simulate_spd_eeprom[15]    = 0x01;    /* wcsbc = 1 */	cfg_simulate_spd_eeprom[27]    = 0x50;    /* tRpNs = 20 ns  */	cfg_simulate_spd_eeprom[29]    = 0x50;    /* tRcdNs = 20 ns */	cfg_simulate_spd_eeprom[30]    = 45;      /* tRasNs */	cfg_simulate_spd_eeprom[18]    = 0x0C;    /* casBit (2,2.5) */	cfg_simulate_spd_eeprom[9]     = 0x75;    /* SDRAM Cycle Time (cas latency 2.5) = 7.5 ns */	cfg_simulate_spd_eeprom[23]    = 0xA0;    /* SDRAM Cycle Time (cas latency 2) = 10 ns */	cfg_simulate_spd_eeprom[25]    = 0x00;    /* SDRAM Cycle Time (cas latency 1.5) = N.A */	cfg_simulate_spd_eeprom[12]    = 0x82;    /* refresh Rate Type: Normal (15.625us) + Self refresh */}long int initdram (int board_type){	long dram_size = 0;	/*	 * First write simulated values in eeprom array for onboard bank 0	 */	init_spd_array();	dram_size = spd_sdram();	return dram_size;}#if defined(CFG_DRAM_TEST)int testdram(void){	unsigned long *mem = (unsigned long *)0;	const unsigned long kend = (1024 / sizeof(unsigned long));	unsigned long k, n;	mtmsr(0);	for (k = 0; k < CFG_KBYTES_SDRAM;	     ++k, mem += (1024 / sizeof(unsigned long))) {		if ((k & 1023) == 0) {			printf("%3d MB\r", k / 1024);		}		memset(mem, 0xaaaaaaaa, 1024);		for (n = 0; n < kend; ++n) {			if (mem[n] != 0xaaaaaaaa) {				printf("SDRAM test fails at: %08x\n",				       (uint) & mem[n]);				return 1;			}		}		memset(mem, 0x55555555, 1024);		for (n = 0; n < kend; ++n) {			if (mem[n] != 0x55555555) {				printf("SDRAM test fails at: %08x\n",				       (uint) & mem[n]);				return 1;			}		}	}	printf("SDRAM test passes\n");	return 0;}#endif/************************************************************************* *  pci_pre_init * *  This routine is called just prior to registering the hose and gives *  the board the opportunity to check things. Returning a value of zero *  indicates that things are bad & PCI initialization should be aborted. * *	Different boards may wish to customize the pci controller structure *	(add regions, override default access routines, etc) or perform *	certain pre-initialization actions. * ************************************************************************/#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)int pci_pre_init(struct pci_controller *hose){	unsigned long addr;	/*-------------------------------------------------------------------------+	  | Set priority for all PLB3 devices to 0.	  | Set PLB3 arbiter to fair mode.	  +-------------------------------------------------------------------------*/	mfsdr(sdr_amp1, addr);	mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);	addr = mfdcr(plb3_acr);	mtdcr(plb3_acr, addr | 0x80000000);	/*-------------------------------------------------------------------------+	  | Set priority for all PLB4 devices to 0.	  +-------------------------------------------------------------------------*/	mfsdr(sdr_amp0, addr);	mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);	addr = mfdcr(plb4_acr) | 0xa0000000;	/* Was 0x8---- */	mtdcr(plb4_acr, addr);	/*-------------------------------------------------------------------------+	  | Set Nebula PLB4 arbiter to fair mode.	  +-------------------------------------------------------------------------*/	/* Segment0 */	addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;	addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;	addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;	addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;	mtdcr(plb0_acr, addr);	/* Segment1 */	addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;	addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;	addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;	addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;	mtdcr(plb1_acr, addr);	return 1;}#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) *//************************************************************************* *  pci_target_init * *	The bootstrap configuration provides default settings for the pci *	inbound map (PIM). But the bootstrap config choices are limited and *	may not be sufficient for a given board. * ************************************************************************/#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)void pci_target_init(struct pci_controller *hose){	/*--------------------------------------------------------------------------+	 * Set up Direct MMIO registers	 *--------------------------------------------------------------------------*/	/*--------------------------------------------------------------------------+	  | PowerPC440 EP PCI Master configuration.	  | Map one 1Gig range of PLB/processor addresses to PCI memory space.	  |   PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF	  |   Use byte reversed out routines to handle endianess.	  | Make this region non-prefetchable.	  +--------------------------------------------------------------------------*/	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */	out32r(PCIX0_PTM1MS, 0x00000001);	/* Memory Size/Attribute */	out32r(PCIX0_PTM1LA, 0);	/* Local Addr. Reg */	out32r(PCIX0_PTM2MS, 0);	/* Memory Size/Attribute */	out32r(PCIX0_PTM2LA, 0);	/* Local Addr. Reg */	/*--------------------------------------------------------------------------+	 * Set up Configuration registers	 *--------------------------------------------------------------------------*/	/* Program the board's subsystem id/vendor id */	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,			      CFG_PCI_SUBSYS_VENDORID);	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);	/* Configure command register as bus master */	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);	/* 240nS PCI clock */	pci_write_config_word(0, PCI_LATENCY_TIMER, 1);	/* No error reporting */	pci_write_config_word(0, PCI_ERREN, 0);	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);}#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) *//************************************************************************* *  pci_master_init * ************************************************************************/#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)void pci_master_init(struct pci_controller *hose){	unsigned short temp_short;	/*--------------------------------------------------------------------------+	  | Write the PowerPC440 EP PCI Configuration regs.	  |   Enable PowerPC440 EP to be a master on the PCI bus (PMM).	  |   Enable PowerPC440 EP to act as a PCI memory target (PTM).	  +--------------------------------------------------------------------------*/	pci_read_config_word(0, PCI_COMMAND, &temp_short);	pci_write_config_word(0, PCI_COMMAND,			      temp_short | PCI_COMMAND_MASTER |			      PCI_COMMAND_MEMORY);}#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) *//************************************************************************* *  is_pci_host * *	This routine is called to determine if a pci scan should be *	performed. With various hardware environments (especially cPCI and *	PPMC) it's insufficient to depend on the state of the arbiter enable *	bit in the strap register, or generic host/adapter assumptions. * *	Rather than hard-code a bad assumption in the general 440 code, the *	440 pci code requires the board to decide at runtime. * *	Return 0 for adapter mode, non-zero for host (monarch) mode. * * ************************************************************************/#if defined(CONFIG_PCI)int is_pci_host(struct pci_controller *hose){	/* Bamboo is always configured as host. */	return (1);}#endif				/* defined(CONFIG_PCI) *//*----------------------------------------------------------------------------+  | is_powerpc440ep_pass1.  +----------------------------------------------------------------------------*/int is_powerpc440ep_pass1(void){	unsigned long pvr;	pvr = get_pvr();	if (pvr == PVR_POWERPC_440EP_PASS1)		return TRUE;	else if (pvr == PVR_POWERPC_440EP_PASS2)		return FALSE;	else {		printf("brdutil error 3\n");		for (;;)			;	}	return(FALSE);}/*----------------------------------------------------------------------------+  | is_nand_selected.  +----------------------------------------------------------------------------*/int is_nand_selected(void){#ifdef CONFIG_BAMBOO_NAND	return TRUE;#else	return FALSE;#endif}/*----------------------------------------------------------------------------+  | config_on_ebc_cs4_is_small_flash => from EPLD  +----------------------------------------------------------------------------*/unsigned char config_on_ebc_cs4_is_small_flash(void){	/* Not implemented yet => returns constant value */	return TRUE;}/*----------------------------------------------------------------------------+  | Ext_bus_cntlr_init.  | Initialize the external bus controller  +----------------------------------------------------------------------------*/void ext_bus_cntlr_init(void){	unsigned long sdr0_pstrp0, sdr0_sdstp1;	unsigned long bootstrap_settings, boot_selection, ebc_boot_size;	int	      computed_boot_device = BOOT_DEVICE_UNKNOWN;	unsigned long ebc0_cs0_bnap_value = 0, ebc0_cs0_bncr_value = 0;	unsigned long ebc0_cs1_bnap_value = 0, ebc0_cs1_bncr_value = 0;	unsigned long ebc0_cs2_bnap_value = 0, ebc0_cs2_bncr_value = 0;	unsigned long ebc0_cs3_bnap_value = 0, ebc0_cs3_bncr_value = 0;	unsigned long ebc0_cs4_bnap_value = 0, ebc0_cs4_bncr_value = 0;	/*-------------------------------------------------------------------------+	  |	  |  PART 1 : Initialize EBC Bank 5	  |  ==============================	  | Bank5 is always associated to the NVRAM/EPLD.	  | It has to be initialized prior to other banks settings computation since	  | some board registers values may be needed	  |	  +-------------------------------------------------------------------------*/	/* NVRAM - FPGA */	mtebc(pb5ap, EBC0_BNAP_NVRAM_FPGA);	mtebc(pb5cr, EBC0_BNCR_NVRAM_FPGA_CS5);	/*-------------------------------------------------------------------------+	  |	  |  PART 2 : Determine which boot device was selected	  |  =========================================	  |	  |  Read Pin Strap Register in PPC440EP	  |  In case of boot from IIC, read Serial Device Strap Register1	  |	  |  Result can either be :	  |   - Boot from EBC 8bits    => SMALL FLASH	  |   - Boot from EBC 16bits   => Large Flash or SRAM	  |   - Boot from NAND Flash	  |   - Boot from PCI	  |	  +-------------------------------------------------------------------------*/	/* Read Pin Strap Register in PPC440EP */	mfsdr(sdr_pstrp0, sdr0_pstrp0);	bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK;	/*-------------------------------------------------------------------------+	  |  PPC440EP Pass1	  +-------------------------------------------------------------------------*/	if (is_powerpc440ep_pass1() == TRUE) {		switch(bootstrap_settings) {		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:			/* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */			/* Boot from Small Flash */			computed_boot_device = BOOT_FROM_SMALL_FLASH;			break;		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:			/* Default Strap Settings 1 : CPU 533 - PLB 133 - Boot PCI 66MHz */			/* Boot from PCI */			computed_boot_device = BOOT_FROM_PCI;			break;		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:			/* Default Strap Settings 2 : CPU 500 - PLB 100 - Boot NDFC16 66MHz */			/* Boot from Nand Flash */			computed_boot_device = BOOT_FROM_NAND_FLASH0;			break;