case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:			/* Default Strap Settings 3 : CPU 333 - PLB 133 - Boot EBC 8 bit 66MHz */			/* Boot from Small Flash */			computed_boot_device = BOOT_FROM_SMALL_FLASH;			break;		case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:		case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:			/* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */			/* Read Serial Device Strap Register1 in PPC440EP */			mfsdr(sdr_sdstp1, sdr0_sdstp1);			boot_selection	= sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;			ebc_boot_size	= sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;			switch(boot_selection) {			case SDR0_SDSTP1_BOOT_SEL_EBC:				switch(ebc_boot_size) {				case SDR0_SDSTP1_EBC_ROM_BS_16BIT:					computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;					break;				case SDR0_SDSTP1_EBC_ROM_BS_8BIT:					computed_boot_device = BOOT_FROM_SMALL_FLASH;					break;				}				break;			case SDR0_SDSTP1_BOOT_SEL_PCI:				computed_boot_device = BOOT_FROM_PCI;				break;			case SDR0_SDSTP1_BOOT_SEL_NDFC:				computed_boot_device = BOOT_FROM_NAND_FLASH0;				break;			}			break;		}	}	/*-------------------------------------------------------------------------+	  |  PPC440EP Pass2	  +-------------------------------------------------------------------------*/	else {		switch(bootstrap_settings) {		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:			/* Default Strap Settings 0 : CPU 400 - PLB 133 - Boot EBC 8 bit 33MHz */			/* Boot from Small Flash */			computed_boot_device = BOOT_FROM_SMALL_FLASH;			break;		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:			/* Default Strap Settings 1 : CPU 333 - PLB 133 - Boot PCI 66MHz */			/* Boot from PCI */			computed_boot_device = BOOT_FROM_PCI;			break;		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:			/* Default Strap Settings 2 : CPU 400 - PLB 100 - Boot NDFC16 33MHz */			/* Boot from Nand Flash */			computed_boot_device = BOOT_FROM_NAND_FLASH0;			break;		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS3:			/* Default Strap Settings 3 : CPU 400 - PLB 100 - Boot EBC 16 bit 33MHz */			/* Boot from Large Flash or SRAM */			computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;			break;		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:			/* Default Strap Settings 4 : CPU 333 - PLB 133 - Boot EBC 16 bit 66MHz */			/* Boot from Large Flash or SRAM */			computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;			break;		case SDR0_PSTRP0_BOOTSTRAP_SETTINGS6:			/* Default Strap Settings 6 : CPU 400 - PLB 100 - Boot PCI 33MHz */			/* Boot from PCI */			computed_boot_device = BOOT_FROM_PCI;			break;		case SDR0_PSTRP0_BOOTSTRAP_IIC_A8_EN:		case SDR0_PSTRP0_BOOTSTRAP_IIC_A4_EN:			/* Default Strap Settings 5-7 */			/* Boot Settings in IIC EEprom address 0xA8 or 0xA4 */			/* Read Serial Device Strap Register1 in PPC440EP */			mfsdr(sdr_sdstp1, sdr0_sdstp1);			boot_selection	= sdr0_sdstp1 & SDR0_SDSTP1_BOOT_SEL_MASK;			ebc_boot_size	= sdr0_sdstp1 & SDR0_SDSTP1_EBC_ROM_BS_MASK;			switch(boot_selection) {			case SDR0_SDSTP1_BOOT_SEL_EBC:				switch(ebc_boot_size) {				case SDR0_SDSTP1_EBC_ROM_BS_16BIT:					computed_boot_device = BOOT_FROM_LARGE_FLASH_OR_SRAM;					break;				case SDR0_SDSTP1_EBC_ROM_BS_8BIT:					computed_boot_device = BOOT_FROM_SMALL_FLASH;					break;				}				break;			case SDR0_SDSTP1_BOOT_SEL_PCI:				computed_boot_device = BOOT_FROM_PCI;				break;			case SDR0_SDSTP1_BOOT_SEL_NDFC:				computed_boot_device = BOOT_FROM_NAND_FLASH0;				break;			}			break;		}	}	/*-------------------------------------------------------------------------+	  |	  |  PART 3 : Compute EBC settings depending on selected boot device	  |  ======   ======================================================	  |	  | Resulting EBC init will be among following configurations :	  |	  |  - Boot from EBC 8bits => boot from SMALL FLASH selected	  |	       EBC-CS0	   = Small Flash	  |	       EBC-CS1,2,3 = NAND Flash or	  |			    Exp.Slot depending on Soft Config	  |	       EBC-CS4	   = SRAM/Large Flash or	  |			    Large Flash/SRAM depending on jumpers	  |	       EBC-CS5	   = NVRAM / EPLD	  |	  |  - Boot from EBC 16bits => boot from Large Flash or SRAM selected	  |	       EBC-CS0	   = SRAM/Large Flash or	  |			     Large Flash/SRAM depending on jumpers	  |	       EBC-CS1,2,3 = NAND Flash or	  |			     Exp.Slot depending on Software Configuration	  |	       EBC-CS4	   = Small Flash	  |	       EBC-CS5	   = NVRAM / EPLD	  |	  |  - Boot from NAND Flash	  |	       EBC-CS0	   = NAND Flash0	  |	       EBC-CS1,2,3 = NAND Flash1	  |	       EBC-CS4	   = SRAM/Large Flash or	  |			     Large Flash/SRAM depending on jumpers	  |	       EBC-CS5	   = NVRAM / EPLD	  |	  |    - Boot from PCI	  |	       EBC-CS0	   = ...	  |	       EBC-CS1,2,3 = NAND Flash or	  |			     Exp.Slot depending on Software Configuration	  |	       EBC-CS4	   = SRAM/Large Flash or	  |			     Large Flash/SRAM or	  |			     Small Flash depending on jumpers	  |	       EBC-CS5	   = NVRAM / EPLD	  |	  +-------------------------------------------------------------------------*/	switch(computed_boot_device) {		/*------------------------------------------------------------------------- */	case BOOT_FROM_SMALL_FLASH:		/*------------------------------------------------------------------------- */		ebc0_cs0_bnap_value = EBC0_BNAP_SMALL_FLASH;		ebc0_cs0_bncr_value = EBC0_BNCR_SMALL_FLASH_CS0;		if ((is_nand_selected()) == TRUE) {			/* NAND Flash */			ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;			ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;			ebc0_cs2_bnap_value = EBC0_BNAP_NAND_FLASH;			ebc0_cs2_bncr_value = EBC0_BNCR_NAND_FLASH_CS2;			ebc0_cs3_bnap_value = 0;			ebc0_cs3_bncr_value = 0;		} else {			/* Expansion Slot */			ebc0_cs1_bnap_value = 0;			ebc0_cs1_bncr_value = 0;			ebc0_cs2_bnap_value = 0;			ebc0_cs2_bncr_value = 0;			ebc0_cs3_bnap_value = 0;			ebc0_cs3_bncr_value = 0;		}		ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;		ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;		break;		/*------------------------------------------------------------------------- */	case BOOT_FROM_LARGE_FLASH_OR_SRAM:		/*------------------------------------------------------------------------- */		ebc0_cs0_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;		ebc0_cs0_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS0;		if ((is_nand_selected()) == TRUE) {			/* NAND Flash */			ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;			ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;			ebc0_cs2_bnap_value = 0;			ebc0_cs2_bncr_value = 0;			ebc0_cs3_bnap_value = 0;			ebc0_cs3_bncr_value = 0;		} else {			/* Expansion Slot */			ebc0_cs1_bnap_value = 0;			ebc0_cs1_bncr_value = 0;			ebc0_cs2_bnap_value = 0;			ebc0_cs2_bncr_value = 0;			ebc0_cs3_bnap_value = 0;			ebc0_cs3_bncr_value = 0;		}		ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;		ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;		break;		/*------------------------------------------------------------------------- */	case BOOT_FROM_NAND_FLASH0:		/*------------------------------------------------------------------------- */		ebc0_cs0_bnap_value = 0;		ebc0_cs0_bncr_value = 0;		ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;		ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;		ebc0_cs2_bnap_value = 0;		ebc0_cs2_bncr_value = 0;		ebc0_cs3_bnap_value = 0;		ebc0_cs3_bncr_value = 0;		/* Large Flash or SRAM */		ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;		ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;		break;		/*------------------------------------------------------------------------- */	case BOOT_FROM_PCI:		/*------------------------------------------------------------------------- */		ebc0_cs0_bnap_value = 0;		ebc0_cs0_bncr_value = 0;		if ((is_nand_selected()) == TRUE) {			/* NAND Flash */			ebc0_cs1_bnap_value = EBC0_BNAP_NAND_FLASH;			ebc0_cs1_bncr_value = EBC0_BNCR_NAND_FLASH_CS1;			ebc0_cs2_bnap_value = 0;			ebc0_cs2_bncr_value = 0;			ebc0_cs3_bnap_value = 0;			ebc0_cs3_bncr_value = 0;		} else {			/* Expansion Slot */			ebc0_cs1_bnap_value = 0;			ebc0_cs1_bncr_value = 0;			ebc0_cs2_bnap_value = 0;			ebc0_cs2_bncr_value = 0;			ebc0_cs3_bnap_value = 0;			ebc0_cs3_bncr_value = 0;		}		if ((config_on_ebc_cs4_is_small_flash()) == TRUE) {			/* Small Flash */			ebc0_cs4_bnap_value = EBC0_BNAP_SMALL_FLASH;			ebc0_cs4_bncr_value = EBC0_BNCR_SMALL_FLASH_CS4;		} else {			/* Large Flash or SRAM */			ebc0_cs4_bnap_value = EBC0_BNAP_LARGE_FLASH_OR_SRAM;			ebc0_cs4_bncr_value = EBC0_BNCR_LARGE_FLASH_OR_SRAM_CS4;		}		break;		/*------------------------------------------------------------------------- */	case BOOT_DEVICE_UNKNOWN:		/*------------------------------------------------------------------------- */		/* Error */		break;	}	/*-------------------------------------------------------------------------+	  | Initialize EBC CONFIG	  +-------------------------------------------------------------------------*/	mtdcr(ebccfga, xbcfg);	mtdcr(ebccfgd, EBC0_CFG_EBTC_DRIVEN	   |	      EBC0_CFG_PTD_ENABLED	  |	      EBC0_CFG_RTC_2048PERCLK	  |	      EBC0_CFG_EMPL_LOW		  |	      EBC0_CFG_EMPH_LOW		  |	      EBC0_CFG_CSTC_DRIVEN	  |	      EBC0_CFG_BPF_ONEDW	  |	      EBC0_CFG_EMS_8BIT		  |	      EBC0_CFG_PME_DISABLED	  |	      EBC0_CFG_PMT_ENCODE(0)	  );	/*-------------------------------------------------------------------------+	  | Initialize EBC Bank 0-4	  +-------------------------------------------------------------------------*/	/* EBC Bank0 */	mtebc(pb0ap, ebc0_cs0_bnap_value);	mtebc(pb0cr, ebc0_cs0_bncr_value);	/* EBC Bank1 */	mtebc(pb1ap, ebc0_cs1_bnap_value);	mtebc(pb1cr, ebc0_cs1_bncr_value);	/* EBC Bank2 */	mtebc(pb2ap, ebc0_cs2_bnap_value);	mtebc(pb2cr, ebc0_cs2_bncr_value);	/* EBC Bank3 */	mtebc(pb3ap, ebc0_cs3_bnap_value);	mtebc(pb3cr, ebc0_cs3_bncr_value);	/* EBC Bank4 */	mtebc(pb4ap, ebc0_cs4_bnap_value);	mtebc(pb4cr, ebc0_cs4_bncr_value);	return;}/*----------------------------------------------------------------------------+  | get_uart_configuration.  +----------------------------------------------------------------------------*/uart_config_nb_t get_uart_configuration(void){	return (L4);}/*----------------------------------------------------------------------------+  | set_phy_configuration_through_fpga => to EPLD  +----------------------------------------------------------------------------*/void set_phy_configuration_through_fpga(zmii_config_t config){	unsigned long fpga_selection_reg;	fpga_selection_reg = in8(FPGA_SELECTION_1_REG) & ~FPGA_SEL_1_REG_PHY_MASK;	switch(config)	{	case ZMII_CONFIGURATION_IS_MII:		fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_MII;		break;	case ZMII_CONFIGURATION_IS_RMII:		fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_RMII;		break;	case ZMII_CONFIGURATION_IS_SMII:		fpga_selection_reg = fpga_selection_reg | FPGA_SEL_1_REG_SMII;		break;	case ZMII_CONFIGURATION_UNKNOWN:	default:		break;	}	out8(FPGA_SELECTION_1_REG,fpga_selection_reg);}/*----------------------------------------------------------------------------+  | scp_selection_in_fpga.  +----------------------------------------------------------------------------*/void scp_selection_in_fpga(void){	unsigned long fpga_selection_2_reg;	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;	fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_SCP;	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);}/*----------------------------------------------------------------------------+  | iic1_selection_in_fpga.  +----------------------------------------------------------------------------*/void iic1_selection_in_fpga(void){	unsigned long fpga_selection_2_reg;	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_IIC1_SCP_SEL_MASK;	fpga_selection_2_reg |= FPGA_SEL2_REG_SEL_IIC1;	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);}/*----------------------------------------------------------------------------+  | dma_a_b_selection_in_fpga.  +----------------------------------------------------------------------------*/void dma_a_b_selection_in_fpga(void){