unsigned long fpga_selection_2_reg;	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_A_B;	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);}/*----------------------------------------------------------------------------+  | dma_a_b_unselect_in_fpga.  +----------------------------------------------------------------------------*/void dma_a_b_unselect_in_fpga(void){	unsigned long fpga_selection_2_reg;	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_A_B;	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);}/*----------------------------------------------------------------------------+  | dma_c_d_selection_in_fpga.  +----------------------------------------------------------------------------*/void dma_c_d_selection_in_fpga(void){	unsigned long fpga_selection_2_reg;	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) | FPGA_SEL2_REG_SEL_DMA_C_D;	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);}/*----------------------------------------------------------------------------+  | dma_c_d_unselect_in_fpga.  +----------------------------------------------------------------------------*/void dma_c_d_unselect_in_fpga(void){	unsigned long fpga_selection_2_reg;	fpga_selection_2_reg = in8(FPGA_SELECTION_2_REG) & ~FPGA_SEL2_REG_SEL_DMA_C_D;	out8(FPGA_SELECTION_2_REG,fpga_selection_2_reg);}/*----------------------------------------------------------------------------+  | usb2_device_selection_in_fpga.  +----------------------------------------------------------------------------*/void usb2_device_selection_in_fpga(void){	unsigned long fpga_selection_1_reg;	fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_DEV_SEL;	out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);}/*----------------------------------------------------------------------------+  | usb2_device_reset_through_fpga.  +----------------------------------------------------------------------------*/void usb2_device_reset_through_fpga(void){	/* Perform soft Reset pulse */	unsigned long fpga_reset_reg;	int i;	fpga_reset_reg = in8(FPGA_RESET_REG);	out8(FPGA_RESET_REG,fpga_reset_reg | FPGA_RESET_REG_RESET_USB20_DEV);	for (i=0; i<500; i++)		udelay(1000);	out8(FPGA_RESET_REG,fpga_reset_reg);}/*----------------------------------------------------------------------------+  | usb2_host_selection_in_fpga.  +----------------------------------------------------------------------------*/void usb2_host_selection_in_fpga(void){	unsigned long fpga_selection_1_reg;	fpga_selection_1_reg = in8(FPGA_SELECTION_1_REG) | FPGA_SEL_1_REG_USB2_HOST_SEL;	out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);}/*----------------------------------------------------------------------------+  | ndfc_selection_in_fpga.  +----------------------------------------------------------------------------*/void ndfc_selection_in_fpga(void){	unsigned long fpga_selection_1_reg;	fpga_selection_1_reg  = in8(FPGA_SELECTION_1_REG) &~FPGA_SEL_1_REG_NF_SELEC_MASK;	fpga_selection_1_reg |= FPGA_SEL_1_REG_NF0_SEL_BY_NFCS1;	fpga_selection_1_reg |= FPGA_SEL_1_REG_NF1_SEL_BY_NFCS2;	out8(FPGA_SELECTION_1_REG,fpga_selection_1_reg);}/*----------------------------------------------------------------------------+  | uart_selection_in_fpga.  +----------------------------------------------------------------------------*/void uart_selection_in_fpga(uart_config_nb_t uart_config){	/* FPGA register */	unsigned char	fpga_selection_3_reg;	/* Read FPGA Reagister */	fpga_selection_3_reg = in8(FPGA_SELECTION_3_REG);	switch (uart_config)	{	case L1:		/* ----------------------------------------------------------------------- */		/* L1 configuration:	UART0 = 8 pins */		/* ----------------------------------------------------------------------- */		/* Configure FPGA */		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG1;		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);		break;	case L2:		/* ----------------------------------------------------------------------- */		/* L2 configuration:	UART0 = 4 pins */		/*			UART1 = 4 pins */		/* ----------------------------------------------------------------------- */		/* Configure FPGA */		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG2;		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);		break;	case L3:		/* ----------------------------------------------------------------------- */		/* L3 configuration:	UART0 = 4 pins */		/*			UART1 = 2 pins */		/*			UART2 = 2 pins */		/* ----------------------------------------------------------------------- */		/* Configure FPGA */		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG3;		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);		break;	case L4:		/* Configure FPGA */		fpga_selection_3_reg	= fpga_selection_3_reg & ~FPGA_SEL3_REG_SEL_UART_CONFIG_MASK;		fpga_selection_3_reg	= fpga_selection_3_reg | FPGA_SEL3_REG_SEL_UART_CONFIG4;		out8(FPGA_SELECTION_3_REG, fpga_selection_3_reg);		break;	default:		/* Unsupported UART configuration number */		for (;;)			;		break;	}}/*----------------------------------------------------------------------------+  | init_default_gpio  +----------------------------------------------------------------------------*/void init_default_gpio(void){	int i;	/* Init GPIO0 */	for(i=0; i<GPIO_MAX; i++)	{		gpio_tab[GPIO0][i].add	  = GPIO0_BASE;		gpio_tab[GPIO0][i].in_out = GPIO_DIS;		gpio_tab[GPIO0][i].alt_nb = GPIO_SEL;	}	/* Init GPIO1 */	for(i=0; i<GPIO_MAX; i++)	{		gpio_tab[GPIO1][i].add	  = GPIO1_BASE;		gpio_tab[GPIO1][i].in_out = GPIO_DIS;		gpio_tab[GPIO1][i].alt_nb = GPIO_SEL;	}	/* EBC_CS_N(5) - GPIO0_10 */	gpio_tab[GPIO0][10].in_out    = GPIO_OUT;	gpio_tab[GPIO0][10].alt_nb    = GPIO_ALT1;	/* EBC_CS_N(4) - GPIO0_9 */	gpio_tab[GPIO0][9].in_out    = GPIO_OUT;	gpio_tab[GPIO0][9].alt_nb    = GPIO_ALT1;}/*----------------------------------------------------------------------------+  | update_uart_ios  +------------------------------------------------------------------------------  |  | Set UART Configuration in PowerPC440EP  |  | +---------------------------------------------------------------------+  | | Configuartion   |	  Connector   | Nb of pins | Pins   | Associated  |  | |	 Number	      |	  Port Name   |	 available | naming |	CORE	  |  | +-----------------+---------------+------------+--------+-------------+  | |	  L1	      |	  Port_A      |	    8	   | UART   | UART core 0 |  | +-----------------+---------------+------------+--------+-------------+  | |	  L2	      |	  Port_A      |	    4	   | UART1  | UART core 0 |  | |	 (L2D)	      |	  Port_B      |	    4	   | UART2  | UART core 1 |  | +-----------------+---------------+------------+--------+-------------+  | |	  L3	      |	  Port_A      |	    4	   | UART1  | UART core 0 |  | |	 (L3D)	      |	  Port_B      |	    2	   | UART2  | UART core 1 |  | |		      |	  Port_C      |	    2	   | UART3  | UART core 2 |  | +-----------------+---------------+------------+--------+-------------+  | |		      |	  Port_A      |	    2	   | UART1  | UART core 0 |  | |	  L4	      |	  Port_B      |	    2	   | UART2  | UART core 1 |  | |	 (L4D)	      |	  Port_C      |	    2	   | UART3  | UART core 2 |  | |		      |	  Port_D      |	    2	   | UART4  | UART core 3 |  | +-----------------+---------------+------------+--------+-------------+  |  |  Involved GPIOs  |  | +------------------------------------------------------------------------------+  | |  GPIO   |	  Aternate 1	 | I/O |  Alternate 2	 | I/O | Alternate 3 | I/O |  | +---------+------------------+-----+-----------------+-----+-------------+-----+  | | GPIO1_2 | UART0_DCD_N	 |  I  | UART1_DSR_CTS_N |  I  | UART2_SOUT  |	O  |  | | GPIO1_3 | UART0_8PIN_DSR_N |  I  | UART1_RTS_DTR_N |  O  | UART2_SIN   |	I  |  | | GPIO1_4 | UART0_8PIN_CTS_N |  I  | NA		 |  NA | UART3_SIN   |	I  |  | | GPIO1_5 | UART0_RTS_N	 |  O  | NA		 |  NA | UART3_SOUT  |	O  |  | | GPIO1_6 | UART0_DTR_N	 |  O  | UART1_SOUT	 |  O  | NA	     |	NA |  | | GPIO1_7 | UART0_RI_N	 |  I  | UART1_SIN	 |  I  | NA	     |	NA |  | +------------------------------------------------------------------------------+  |  |  +----------------------------------------------------------------------------*/void update_uart_ios(uart_config_nb_t uart_config){	switch (uart_config)	{	case L1:		/* ----------------------------------------------------------------------- */		/* L1 configuration:	UART0 = 8 pins */		/* ----------------------------------------------------------------------- */		/* Update GPIO Configuration Table */		gpio_tab[GPIO1][2].in_out = GPIO_IN;		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT1;		gpio_tab[GPIO1][3].in_out = GPIO_IN;		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT1;		gpio_tab[GPIO1][4].in_out = GPIO_IN;		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;		gpio_tab[GPIO1][5].in_out = GPIO_OUT;		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;		gpio_tab[GPIO1][6].in_out = GPIO_OUT;		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT1;		gpio_tab[GPIO1][7].in_out = GPIO_IN;		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT1;		break;	case L2:		/* ----------------------------------------------------------------------- */		/* L2 configuration:	UART0 = 4 pins */		/*			UART1 = 4 pins */		/* ----------------------------------------------------------------------- */		/* Update GPIO Configuration Table */		gpio_tab[GPIO1][2].in_out = GPIO_IN;		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT2;		gpio_tab[GPIO1][3].in_out = GPIO_OUT;		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT2;		gpio_tab[GPIO1][4].in_out = GPIO_IN;		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;		gpio_tab[GPIO1][5].in_out = GPIO_OUT;		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;		gpio_tab[GPIO1][6].in_out = GPIO_OUT;		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;		gpio_tab[GPIO1][7].in_out = GPIO_IN;		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;		break;	case L3:		/* ----------------------------------------------------------------------- */		/* L3 configuration:	UART0 = 4 pins */		/*			UART1 = 2 pins */		/*			UART2 = 2 pins */		/* ----------------------------------------------------------------------- */		/* Update GPIO Configuration Table */		gpio_tab[GPIO1][2].in_out = GPIO_OUT;		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;		gpio_tab[GPIO1][3].in_out = GPIO_IN;		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;		gpio_tab[GPIO1][4].in_out = GPIO_IN;		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT1;		gpio_tab[GPIO1][5].in_out = GPIO_OUT;		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT1;		gpio_tab[GPIO1][6].in_out = GPIO_OUT;		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;		gpio_tab[GPIO1][7].in_out = GPIO_IN;		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;		break;	case L4:		/* ----------------------------------------------------------------------- */		/* L4 configuration:	UART0 = 2 pins */		/*			UART1 = 2 pins */		/*			UART2 = 2 pins */		/*			UART3 = 2 pins */		/* ----------------------------------------------------------------------- */		/* Update GPIO Configuration Table */		gpio_tab[GPIO1][2].in_out = GPIO_OUT;		gpio_tab[GPIO1][2].alt_nb = GPIO_ALT3;		gpio_tab[GPIO1][3].in_out = GPIO_IN;		gpio_tab[GPIO1][3].alt_nb = GPIO_ALT3;		gpio_tab[GPIO1][4].in_out = GPIO_IN;		gpio_tab[GPIO1][4].alt_nb = GPIO_ALT3;		gpio_tab[GPIO1][5].in_out = GPIO_OUT;		gpio_tab[GPIO1][5].alt_nb = GPIO_ALT3;		gpio_tab[GPIO1][6].in_out = GPIO_OUT;		gpio_tab[GPIO1][6].alt_nb = GPIO_ALT2;		gpio_tab[GPIO1][7].in_out = GPIO_IN;		gpio_tab[GPIO1][7].alt_nb = GPIO_ALT2;		break;	default:		/* Unsupported UART configuration number */		printf("ERROR - Unsupported UART configuration number.\n\n");		for (;;)			;		break;	}	/* Set input Selection Register on Alt_Receive for UART Input Core */	out32(GPIO1_IS1L, (in32(GPIO1_IS1L) | 0x0FC30000));	out32(GPIO1_IS2L, (in32(GPIO1_IS2L) | 0x0C030000));	out32(GPIO1_IS3L, (in32(GPIO1_IS3L) | 0x03C00000));}/*----------------------------------------------------------------------------+  | update_ndfc_ios(void).  +----------------------------------------------------------------------------*/void update_ndfc_ios(void){	/* Update GPIO Configuration Table */	gpio_tab[GPIO0][6].in_out = GPIO_OUT;	    /* EBC_CS_N(1) */	gpio_tab[GPIO0][6].alt_nb = GPIO_ALT1;#if 0	gpio_tab[GPIO0][7].in_out = GPIO_OUT;	    /* EBC_CS_N(2) */	gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;	gpio_tab[GPIO0][7].in_out = GPIO_OUT;	    /* EBC_CS_N(3) */	gpio_tab[GPIO0][7].alt_nb = GPIO_ALT1;#endif}/*----------------------------------------------------------------------------+  | update_zii_ios(void).  +----------------------------------------------------------------------------*/void update_zii_ios(void)