volatile immap_t *immap = (immap_t *)CFG_IMMR;	puts("Initializing\n");#if defined(CONFIG_DDR_DLL)	{		/*		 * Work around to stabilize DDR DLL MSYNC_IN.		 * Errata DDR9 seems to have been fixed.		 * This is now the workaround for Errata DDR11:		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0		 */		volatile ccsr_gur_t *gur= &immap->im_gur;		gur->ddrdllcr = 0x81000000;		asm("sync;isync;msync");		udelay(200);	}#endif	dram_size = spd_sdram();#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)	/*	 * Initialize and enable DDR ECC.	 */	ddr_enable_ecc(dram_size);#endif	/*	 * SDRAM Initialization	 */	sdram_init();	puts("    DDR: ");	return dram_size;}/* * Initialize Local Bus */voidlocal_bus_init(void){	volatile immap_t *immap = (immap_t *)CFG_IMMR;	volatile ccsr_gur_t *gur = &immap->im_gur;	volatile ccsr_lbc_t *lbc = &immap->im_lbc;	uint clkdiv;	uint lbc_hz;	sys_info_t sysinfo;	uint temp_lbcdll;	/*	 * Errata LBC11.	 * Fix Local Bus clock glitch when DLL is enabled.	 *	 * If localbus freq is < 66Mhz, DLL bypass mode must be used.	 * If localbus freq is > 133Mhz, DLL can be safely enabled.	 * Between 66 and 133, the DLL is enabled with an override workaround.	 */	get_sys_info(&sysinfo);	clkdiv = lbc->lcrr & 0x0f;	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;	if (lbc_hz < 66) {		lbc->lcrr |= 0x80000000;	/* DLL Bypass */	} else if (lbc_hz >= 133) {		lbc->lcrr &= (~0x80000000);		/* DLL Enabled */	} else {		lbc->lcrr &= (~0x8000000);	/* DLL Enabled */		udelay(200);		/*		 * Sample LBC DLL ctrl reg, upshift it to set the		 * override bits.		 */		temp_lbcdll = gur->lbcdllcr;		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);		asm("sync;isync;msync");	}}/* * Initialize SDRAM memory on the Local Bus. */voidsdram_init(void){#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)	uint idx;	volatile immap_t *immap = (immap_t *)CFG_IMMR;	volatile ccsr_lbc_t *lbc = &immap->im_lbc;	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;	uint cpu_board_rev;	uint lsdmr_common;	puts("    SDRAM: ");	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");	/*	 * Setup SDRAM Base and Option Registers	 */	lbc->or2 = CFG_OR2_PRELIM;	asm("msync");	lbc->br2 = CFG_BR2_PRELIM;	asm("msync");	lbc->lbcr = CFG_LBC_LBCR;	asm("msync");	lbc->lsrt = CFG_LBC_LSRT;	lbc->mrtpr = CFG_LBC_MRTPR;	asm("msync");	/*	 * Determine which address lines to use baed on CPU board rev.	 */	cpu_board_rev = get_cpu_board_revision();	lsdmr_common = CFG_LBC_LSDMR_COMMON;	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {		lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {		lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;	} else {		/*		 * Assume something unable to identify itself is		 * really old, and likely has lines 16/17 mapped.		 */		lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;	}	/*	 * Issue PRECHARGE ALL command.	 */	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;	asm("sync;msync");	*sdram_addr = 0xff;	ppcDcbf((unsigned long) sdram_addr);	udelay(100);	/*	 * Issue 8 AUTO REFRESH commands.	 */	for (idx = 0; idx < 8; idx++) {		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;		asm("sync;msync");		*sdram_addr = 0xff;		ppcDcbf((unsigned long) sdram_addr);		udelay(100);	}	/*	 * Issue 8 MODE-set command.	 */	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;	asm("sync;msync");	*sdram_addr = 0xff;	ppcDcbf((unsigned long) sdram_addr);	udelay(100);	/*	 * Issue NORMAL OP command.	 */	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;	asm("sync;msync");	*sdram_addr = 0xff;	ppcDcbf((unsigned long) sdram_addr);	udelay(200);    /* Overkill. Must wait > 200 bus cycles */#endif	/* enable SDRAM init */}#if defined(CFG_DRAM_TEST)inttestdram(void){	uint *pstart = (uint *) CFG_MEMTEST_START;	uint *pend = (uint *) CFG_MEMTEST_END;	uint *p;	printf("Testing DRAM from 0x%08x to 0x%08x\n",	       CFG_MEMTEST_START,	       CFG_MEMTEST_END);	printf("DRAM test phase 1:\n");	for (p = pstart; p < pend; p++)		*p = 0xaaaaaaaa;	for (p = pstart; p < pend; p++) {		if (*p != 0xaaaaaaaa) {			printf ("DRAM test fails at: %08x\n", (uint) p);			return 1;		}	}	printf("DRAM test phase 2:\n");	for (p = pstart; p < pend; p++)		*p = 0x55555555;	for (p = pstart; p < pend; p++) {		if (*p != 0x55555555) {			printf ("DRAM test fails at: %08x\n", (uint) p);			return 1;		}	}	printf("DRAM test passed.\n");	return 0;}#endif#if defined(CONFIG_PCI)/* For some reason the Tundra PCI bridge shows up on itself as a * different device.  Work around that by refusing to configure it. */void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { }static struct pci_config_table pci_mpc85xxcds_config_table[] = {	{0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}},	{0x1106, 0x0686, PCI_ANY_ID, 1, 2, 0, mpc85xx_config_via, {0,0,0}},	{0x1106, 0x0571, PCI_ANY_ID, 1, 2, 1, mpc85xx_config_via_usbide, {0,0,0}},	{0x1105, 0x3038, PCI_ANY_ID, 1, 2, 2, mpc85xx_config_via_usb, {0,0,0}},	{0x1106, 0x3038, PCI_ANY_ID, 1, 2, 3, mpc85xx_config_via_usb2, {0,0,0}},	{0x1106, 0x3058, PCI_ANY_ID, 1, 2, 5, mpc85xx_config_via_power, {0,0,0}},	{0x1106, 0x3068, PCI_ANY_ID, 1, 2, 6, mpc85xx_config_via_ac97, {0,0,0}}};static struct pci_controller hose[] = {	{ config_table: pci_mpc85xxcds_config_table,},#ifdef CONFIG_MPC85XX_PCI2	{},#endif};#endif	/* CONFIG_PCI */voidpci_init_board(void){#ifdef CONFIG_PCI	pci_mpc85xx_init(hose);#endif}