?? dabort.s
字號:
[ PassRegDumpAddr
ArgVar SETA ArgVar-1
ArgVar2 SETA ArgVar :AND: 3
MOV R$ArgVar2, R8
[ ArgVar2 = 0 :LAND: ArgVar <> 0
ArgString SETS ArgString :RIGHT: (:LEN:ArgString - 1)
STMFD R13!,{$ArgString}
ArgString SETS ""
]
]
[ PassInstrAddr
ArgVar SETA ArgVar-1
ArgVar2 SETA ArgVar :AND: 3
ArgString SETS ",R$ArgVar2" :CC: ArgString
MOV R$ArgVar2, R4
[ ArgVar2 = 0 :LAND: ArgVar <> 0
ArgString SETS ArgString :RIGHT: (:LEN:ArgString - 1)
STMFD R13!,{$ArgString}
ArgString SETS ""
]
]
[ PassSPSR
ArgVar SETA ArgVar-1
ArgVar2 SETA ArgVar :AND: 3
ArgString SETS ",R$ArgVar2" :CC: ArgString
MOV R$ArgVar2, R5
[ ArgVar2 = 0 :LAND: ArgVar <> 0
ArgString SETS ArgString :RIGHT: (:LEN:ArgString - 1)
STMFD R13!,{$ArgString}
ArgString SETS ""
]
]
ArgVar SETA ArgVar-1
ArgVar2 SETA ArgVar :AND: 3
ArgString SETS ",R$ArgVar2" :CC: ArgString
MOV R$ArgVar2, R6
[ ArgVar2 = 0 :LAND: ArgVar <> 0
ArgString SETS ArgString :RIGHT: (:LEN:ArgString - 1)
STMFD R13!,{$ArgString}
ArgString SETS ""
]
; Check all the above conditional assembly is self-consistent.
ASSERT ArgVar = 0
; Finally, we're ready to issue the procedure call.
;
; *** Live register values at this point are:
; R0-R3: Arguments as appropriate
; R4: Pointer to aborting instruction
; R5: SPSR value
; R6: Error code
; R7: Transfer address
; R8: R13_abort value (if calling in other than abort mode)
; R13: Stack pointer (pointing to any arguments over four)
HandlerInternalMacro
; If we needed to use some stack for the argument list, release it.
[ ArgCount > 4
ADD R13, R13, #(ArgCount-4)*4
]
; If we switched modes, restore abort mode and R13_abort.
[ HandlerCallMode <> "Abort"
MRS R3, CPSR
BIC R3, R3, #Mode_FullMask
ORR R3, R3, #Mode_Abort
MSR CPSR$all_fields, R3
MOV R13, R8
]
; Deal with the OS-specific handler's return value
; ================================================
[ ReturnNormal
; Code to return and retry the aborting instruction
; -------------------------------------------------
;
; *** Live register values at this point are:
; R0: Return value from OS-specific handler
; R4: Pointer to aborting instruction
; R5: SPSR value
; R6: Error code
; R13: Stack pointer (pointing to register dump)
CMP R0, #DABORT_RETVAL_NORMAL
BNE NotReturnNormal
; This return value isn't valid unless there was no error originally.
CMP R6, #DABORT_ERROR_NONE
BNE ReturnInvalid
; We need to take care about how we return if we're to get all the
; registers right. First thing to do is restore the banked registers -
; this needs the same precautions about user modes as the
; corresponding entry code.
ADD R7, R13, #8*4 ; Place to find reg values
ANDS R1, R5, #Mode_MainMask
ASSERT (Mode_User:AND:Mode_MainMask) = 0
LDMEQIA R7, {R8-R14}^
BEQ RegsRestored_Normal
MRS R2, CPSR
BIC R3, R2, #Mode_MainMask
ORR R1, R3, R1
MSR CPSR$all_fields, R1
LDMIA R7, {R8-R14}
MSR CPSR$all_fields, R2
RegsRestored_Normal
; PC value wanted is the address of the aborting instruction, CPSR
; value wanted is the entry SPSR value.
STR R4, [R13, #14*4]
MSR SPSR$all_fields, R5
; Now we're ready to restore the rest of the registers and return.
LDMIA R13, {R0-R7}
ADD R13, R13, #14*4
LDMIA R13!, {PC}^
LTORG
NotReturnNormal
]
[ ReturnUndef <> ""
; Code to fake an undefined instruction trap
; ------------------------------------------
;
; *** Live register values at this point are:
; R0: Return value from OS-specific handler
; R4: Pointer to aborting instruction
; R5: SPSR value
; R6: Error code
; R13: Stack pointer (pointing to register dump)
CMP R0, #DABORT_RETVAL_UNDEF
BNE NotReturnUndef
; There are a number of CPSR manipulations in what follows, so get it
; into a register. Also produce a "main mode number blanked" version
; of it.
MRS R2, CPSR
BIC R3, R2, #Mode_MainMask
; We need to take care about how we return if we're to get all the
; registers right. First thing to do is restore the banked registers -
; this needs the same precautions about user modes as the
; corresponding entry code.
ADD R7, R13, #8*4 ; Place to find reg values
ANDS R1, R5, #Mode_MainMask
ASSERT (Mode_User:AND:Mode_MainMask) = 0
LDMEQIA R7, {R8-R14}^
BEQ RegsRestored_Undef
ORR R1, R3, R1
MSR CPSR$all_fields, R1
LDMIA R7, {R8-R14}
; N.B. No need to shift back to the original mode at this point.
RegsRestored_Undef
; Next, we need to shift over to undefined instruction mode in order
; to get R14_undef and SPSR_undef right, then shift back so that we
; can do the rest of the work on the abort mode stack.
ORR R1, R3, #Mode_Undef
MSR CPSR$all_fields, R1
MSR SPSR$all_fields, R5
ADD R14, R4, #PCOffset_Undef
MSR CPSR$all_fields, R2
; Now put the CPSR we want to end up with in SPSR_abort, and the PC
; value we want to end up with in the top used word of the stack.
BIC R0, R5, #Mode_FullMask + T_bit
ORR R0, R0, #Mode_Undef + I_bit
MSR SPSR$all_fields, R0
LDR R0, =$ReturnUndef
STR R0, [R13, #14*4]
; Now we're ready to finish "returning".
LDMIA R13, {R0-R7}
ADD R13, R13, #14*4
LDMIA R13!, {PC}^
LTORG
NotReturnUndef
]
[ ReturnToNext <> ""
; Code to chain to a second data abort handler
; --------------------------------------------
;
; *** Live register values at this point are:
; R0: Return value from OS-specific handler
; R4: Pointer to aborting instruction
; R5: SPSR value
; R6: Error code
; R13: Stack pointer (pointing to register dump)
CMP R0, #DABORT_RETVAL_TONEXT
BNE NotReturnToNext
; This return value isn't valid unless there was no error originally.
CMP R6, #DABORT_ERROR_NONE
BNE ReturnInvalid
; We need to take care about how we return if we're to get all the
; registers right. First thing to do is restore the banked registers -
; this needs the same precautions about user modes as the
; corresponding entry code.
ADD R7, R13, #8*4 ; Place to find reg values
ANDS R1, R5, #Mode_MainMask
ASSERT (Mode_User:AND:Mode_MainMask) = 0
LDMEQIA R7, {R8-R14}^
BEQ RegsRestored_ToNext
MRS R2, CPSR
BIC R3, R2, #Mode_MainMask
ORR R1, R3, R1
MSR CPSR$all_fields, R1
LDMIA R7, {R8-R14}
MSR CPSR$all_fields, R2
RegsRestored_ToNext
; Restore R14_abort, SPSR_abort and the CPSR to their entry values.
ADD R14, R4, #PCOffset_DAbort
MSR SPSR$all_fields, R5
BIC R0, R5, #Mode_FullMask + T_bit
ORR R0, R0, #Mode_Abort + I_bit
MSR CPSR$all_fields, R0
; Now put the PC value we want to end up with in the top used word of
; the stack.
IMPORT $ReturnToNext
LDR R0, =$ReturnToNext
STR R0, [R13, #14*4]
; Now we're ready to finish "returning".
LDMIA R13, {R0-R7}
ADD R13, R13, #14*4
LDMIA R13!, {PC}
LTORG
NotReturnToNext
]
[ ReturnAddress
; Code to transfer to the R0-specified address
; --------------------------------------------
;
; *** Live register values at this point are:
; R0: Return value from OS-specific handler
; R4: Pointer to aborting instruction
; R5: SPSR value
; R6: Error code
; R13: Stack pointer (pointing to register dump)
;
; We need to take care about how we return if we're to get all the
; registers right. First thing to do is restore the banked registers
; to the correct mode's registers. Also set SPSR_abort to produce the
; desired final mode, if it isn't abort mode.
ADD R7, R13, #8*4 ; Place to find reg values
[ HandlerCallMode = "Abort"
LDMIA R7, {R8-R14}
|
MRS R2, CPSR
BIC R1, R2, #Mode_FullMask
ORR R1, R1, #Mode_Callee
MSR SPSR$all_fields, R1
MSR CPSR$all_fields, R1
LDMIA R7, {R8-R14}
MSR CPSR$all_fields, R2
]
; Now put the PC value we want to end up with in the top used word of
; the stack.
STR R0, [R13, #14*4]
; Now we're ready to finish "returning", with a mode change if
; necessary.
LDMIA R13, {R0-R7}
ADD R13, R13, #14*4
[ HandlerCallMode = "Abort"
LDMIA R13!, {PC}
|
LDMIA R13!, {PC}^
]
LTORG
]
[ (:LNOT:ReturnAddress) \
:LOR: ReturnNormal \
:LOR: (ReturnToNext <> "")
; Code to deal with invalid requests
; ----------------------------------
;
; This code can either be fallen through to (if the "ReturnAddress"
; option isn't requested), or branched to from the "ReturnNormal" or
; "ReturnToNext" code.
ReturnInvalid
; *** Live register values at this point are:
; R0: Return value from OS-specific handler
; R4: Pointer to aborting instruction
; R5: SPSR value
; R6: Error code
; R13: Stack pointer (pointing to register dump)
;
; We need to issue a second call to the OS-specific handler at this
; point, with the "bad request" error code as its first parameter. The
; remaining parameters can be junk, so will simply be whatever happens
; to be in the registers concerned. (Most will in fact be OK.)
MOV R6, #DABORT_ERROR_BAD_REQUEST
B CallOSHandlerWithError
LTORG
]
[ AbortModelInit <> ""
Initialisation_Handler
; Special handler for initialisation routine
; ==========================================
;
; *** Live register values at this point are:
;
; R4: Pointer to aborting instruction
; R5: SPSR value
; R6: Address of abort model variable
; R8: Abort model variable value
; R13: Stack pointer (pointing to register dump)
;
; The abort model identifier is initialised to 0x40000000. Each entry
; to this handler shifts the value left by one bit, shifting in a zero
; if the base register was not changed and a 1 if it was. After two
; such entries, the high order bit is shifted out and we should be in
; a normal abort model. The first time round is done with an LDR
; instruction, the second with an LDM, in order to test the behaviour
; for both single and multiple transfers (needed to distinguish the
; "early aborts" model).
; Both instructions will ?? 快捷鍵說明
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