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;******************************************************************************
;*
;* System On Chip(SOC)
;*
;* Copyright (c) 2002 Software Center, Samsung Electronics, Inc.
;* Copyright (c) 2002 Mobile Solution Project Team, Samsung Electronics, Inc.
;* All rights reserved.
;*
;* This software is the confidential and proprietary information of Samsung
;* Electronics, Inc("Confidential Information"). You Shall not disclose such
;* Confidential Information and shall use it only in accordance with the terms
;* of the license agreement you entered into Samsung.
;*
;******************************************************************************
OPT 2
INCLUDE kxarm.h
INCLUDE reg2440.a
OPT 1
OPT 128
;---------------------------------------------------------------------------
; 4 LED light function
; The LEDs are located below AMD Flash ROM
MACRO
LED_ON $data
LDR r10, =0x56000054
LDR r11, =$data
MOV r11, r11, lsl #4
STR r11, [r10]
MEND
;---------------------------------------------------------------------------
; 4 LED light function
; The LEDs are located below AMD Flash ROM
MACRO
VLED_ON $data
LDR r10, =0xB1600054
LDR r11, =$data
MOV r11, r11, lsl #4
STR r11, [r10]
MEND
;---------------------------------------------------------------------------
IMPORT KernelStart
IMPORT ARMClearUTLB
IMPORT ARMFlushICache
IMPORT ARMFlushDCache
EXPORT SelfRefreshAndPowerOff
EXPORT SelfRefreshAndPowerOff2
; for S3C2440 v0.17 board
; 300MHz -> 1.1 +- 0.05 Volt
; 400MHz -> 1.2 +- 0.05 Volt
; 533MHz -> 1.35 +- 0.05 Volt
; /////////////////////////////////////////
; // D4 D3 D2 D1 D0
; // 0 1 0 0 0 // 1.35V
; // 0 1 0 0 1 // 1.30V
; // 0 1 0 1 0 // 1.25V
; // 0 1 0 1 1 // 1.20V
; // 0 1 1 0 0 // 1.15V
; // 0 1 1 0 1 // 1.10V
; // 0 1 1 1 0 // 1.05V
; // 0 1 1 1 1 // 1.00V
; // 1 0 0 0 1 // 0.95V
; // 1 0 0 1 1 // 0.90V
; // 1 0 1 0 1 // 0.85V
; // 1 0 1 1 1 // 0.80V
GBLA FIN
FIN SETA 12 ; 12, 16
GBLA S2440A
S2440A SETA 1 ; 0 = S2440X, 1 = S2440A
;FCLK EQU (400)
;PLLVAL EQU ((((92)<<12) + (1<<4) + 0x0))
;FCLK EQU (533)
;PLLVAL EQU (((214 << 12) + (3 << 4) + 0))
[ FIN = 12 ;
GBLA CLKVAL
;CLKVAL SETA 300
CLKVAL SETA 400
[ CLKVAL = 300
FCLK EQU (300)
[ S2440A = 1 ; S2440A
PLLVAL EQU (((67 << 12) + (1 << 4) + 1))
| ; S2440X
PLLVAL EQU (((67 << 12) + (1 << 4) + 0))
]
CLKDIVVAL EQU 7 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.05 V
D3VAL EQU 1
D2VAL EQU 1
D1VAL EQU 1
D0VAL EQU 0
]
[ CLKVAL = 400
FCLK EQU (400)
[ S2440A = 1 ; S2440A
PLLVAL EQU (((92 << 12) + (1 << 4) + 1))
| ; S2440X
PLLVAL EQU (((92 << 12) + (1 << 4) + 0))
]
CLKDIVVAL EQU 5 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.3V
D3VAL EQU 1
D2VAL EQU 0
D1VAL EQU 0
D0VAL EQU 1
]
UPLLVAL EQU (((56 << 12) + (2 << 4) + 2))
] ; FIN = OSC_12MHZ
[ FIN = 16
GBLA CLKVAL
;CLKVAL SETA 296
CLKVAL SETA 399
;CLKVAL SETA 530
[ CLKVAL = 296
FCLK EQU (296)
[ S2440A = 1 ; S2440A
PLLVAL EQU (((97 << 12) + (1 << 4) + 2))
| ; S2440X
PLLVAL EQU (((97 << 12) + (1 << 4) + 1))
]
CLKDIVVAL EQU 7 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.05 V
D3VAL EQU 1
D2VAL EQU 1
D1VAL EQU 1
D0VAL EQU 0
]
[ CLKVAL = 399
FCLK EQU (399)
[ S2440A = 1 ; S2440A
PLLVAL EQU (((110 << 12) + (3 << 4) + 1))
| ; S2440X
PLLVAL EQU (((110 << 12) + (3 << 4) + 0))
]
CLKDIVVAL EQU 7 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.3V
D3VAL EQU 1
D2VAL EQU 0
D1VAL EQU 0
D0VAL EQU 1
]
[ CLKVAL = 530
FCLK EQU (530)
[ S2440A = 1 ; S2440A
PLLVAL EQU (((86 << 12) + (1 << 4) + 1))
| ; S2440X
PLLVAL EQU (((86 << 12) + (1 << 4) + 0))
]
CLKDIVVAL EQU 5 ; 0x0 = 1:1:1, 0x1 = 1:1:2, 0x2 = 1:2:2, 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
D4VAL EQU 0 ; 1.35 V
D3VAL EQU 1
D2VAL EQU 0
D1VAL EQU 0
D0VAL EQU 0
]
UPLLVAL EQU (((60 << 12) + (0x4 << 4) + 0x2))
] ; FIN = OSC_16MHZ
R1_iA EQU (1 << 31)
R1_nF EQU (1 << 30)
; Data Cache Characteristics.
;
DCACHE_LINES_PER_SET_BITS EQU 6
DCACHE_LINES_PER_SET EQU 64
DCACHE_NUM_SETS EQU 8
DCACHE_SET_INDEX_BIT EQU (32 - DCACHE_LINES_PER_SET_BITS)
DCACHE_LINE_SIZE EQU 32
SLEEPDATA_BASE_VIRTUAL EQU 0xAC024000 ; keep in sync w/ config.bib
SLEEPDATA_BASE_PHYSICAL EQU 0x30024000
WORD_SIZE EQU (4)
SleepState_Data_Start EQU (0)
SleepState_WakeAddr EQU (SleepState_Data_Start )
SleepState_MMUCTL EQU (SleepState_WakeAddr + WORD_SIZE )
SleepState_MMUTTB EQU (SleepState_MMUCTL + WORD_SIZE )
SleepState_MMUDOMAIN EQU (SleepState_MMUTTB + WORD_SIZE )
SleepState_SVC_SP EQU (SleepState_MMUDOMAIN + WORD_SIZE )
SleepState_SVC_SPSR EQU (SleepState_SVC_SP + WORD_SIZE )
SleepState_FIQ_SPSR EQU (SleepState_SVC_SPSR + WORD_SIZE )
SleepState_FIQ_R8 EQU (SleepState_FIQ_SPSR + WORD_SIZE )
SleepState_FIQ_R9 EQU (SleepState_FIQ_R8 + WORD_SIZE )
SleepState_FIQ_R10 EQU (SleepState_FIQ_R9 + WORD_SIZE )
SleepState_FIQ_R11 EQU (SleepState_FIQ_R10 + WORD_SIZE )
SleepState_FIQ_R12 EQU (SleepState_FIQ_R11 + WORD_SIZE )
SleepState_FIQ_SP EQU (SleepState_FIQ_R12 + WORD_SIZE )
SleepState_FIQ_LR EQU (SleepState_FIQ_SP + WORD_SIZE )
SleepState_ABT_SPSR EQU (SleepState_FIQ_LR + WORD_SIZE )
SleepState_ABT_SP EQU (SleepState_ABT_SPSR + WORD_SIZE )
SleepState_ABT_LR EQU (SleepState_ABT_SP + WORD_SIZE )
SleepState_IRQ_SPSR EQU (SleepState_ABT_LR + WORD_SIZE )
SleepState_IRQ_SP EQU (SleepState_IRQ_SPSR + WORD_SIZE )
SleepState_IRQ_LR EQU (SleepState_IRQ_SP + WORD_SIZE )
SleepState_UND_SPSR EQU (SleepState_IRQ_LR + WORD_SIZE )
SleepState_UND_SP EQU (SleepState_UND_SPSR + WORD_SIZE )
SleepState_UND_LR EQU (SleepState_UND_SP + WORD_SIZE )
SleepState_SYS_SP EQU (SleepState_UND_LR + WORD_SIZE )
SleepState_SYS_LR EQU (SleepState_SYS_SP + WORD_SIZE )
SleepState_Data_End EQU (SleepState_SYS_LR + WORD_SIZE )
SLEEPDATA_SIZE EQU (SleepState_Data_End - SleepState_Data_Start) / 4
MMU_CTL_MASK EQU 0x3FFF0000
MMU_TTB_MASK EQU 0x00003FFF
MMU_ID_MASK EQU 0xFFFFFFF0
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80
F_Bit EQU 0x40
BIT_SELFREFRESH EQU (1<<22)
HandleFIQ EQU 0x33ffff1c
;**
; * StartUp - Image EntryPoint
; *
; * @return .
; * @param .
; *
STARTUPTEXT
LEAF_ENTRY StartUp
1 b ResetHandler
b %B1 ;handler for Undefined mode
b %B1 ;handler for SWI interrupt
b %B1 ;handler for PAbort
b %B1 ;handler for DAbort
b %B1 ;reserved
b %B1 ;handler for IRQ interrupt
;b HandlerFIQ ;handler for FIQ interrupt
ENTER_POWER_OFF ;FIQ Handler
; LED_ON 0x4
ldr r0,=GPFCON
ldr r1,=0x5500
str r1,[r0]
ldr r0,=GPFDAT
ldr r1,=0x20
str r1,[r0]
ldr r5,=REFRESH
ldr r6,[r5]
orr r6, r6, #BIT_SELFREFRESH
ldr r3,=MISCCR
ldr r4,[r3]
orr r4,r4,#(3<<17)
bic r4,r4, #(7 << 20)
orr r4,r4, #(6 << 20)
ldr r2,=0x7fff8
ldr r1,=CLKCON
mov r0,#16
b _EPO ;This code isn't needed for code on the ROM
ALIGN 32
_EPO
1 str r6, [r5] ;Enable SDRAM self-refresh
2 subs r0,r0,#1 ;Wait until self-refresh is issued,which may not be needed.
bne %B2
str r4,[r3] ;Make sure that SCLK0:SCLK->0, SCLK1:SCLK->0, SCKE=L during boot-up
str r2,[r1] ;CPU will enter into POWER_OFF mode.
b .
LTORG
ResetHandler
; LED_ON 0xa
; for smdk2440 v0.17 board 533Mhz (by shlim 031107)
[ {FALSE}
ldr r0, = GPBDAT ; D4
ldr r1, [r0]
ldr r2, = 0x77f
and r1, r1, r2
ldr r2, = (0<<7)
orr r1, r1, r2
str r1, [r0]
]
ldr r0, = GPFDAT ; D3~0
ldr r1, [r0]
ldr r2, = 0x0f
and r1, r1, r2
ldr r2, = (1<<7)
orr r1, r1, r2
ldr r2, = (0<<6)
orr r1, r1, r2
ldr r2, = (0<<5)
orr r1, r1, r2
ldr r2, = (0<<4)
orr r1, r1, r2
str r1, [r0]
[ {FALSE}
ldr r0, = GPBCON ; GPB7: Output
ldr r1, [r0]
ldr r2, = 0x3f3fff
and r1, r1, r2
ldr r2, = (1<<14)
orr r1, r1, r2
str r1, [r0]
]
ldr r0, = GPFCON ; GPF4~7: Output
ldr r1, [r0]
ldr r2, = 0x00ff
and r1, r1, r2
ldr r2, = 0x5500
orr r1, r1, r2
str r1, [r0]
[ {FALSE}
ldr r0, = GPBDAT ; Latch enable
ldr r1, [r0]
ldr r2, = ~(0<<8)
and r1, r1, r2
str r1, [r0]
ldr r0, = GPBCON ; GPB8: Output
ldr r1, [r0]
ldr r2, = 0x3cffff
and r1, r1, r2
ldr r2, = (1<<16)
orr r1, r1, r2
str r1, [r0]
ldr r0, = GPBDAT ; Output enable
ldr r1, [r0]
ldr r2, = (1<<10)
orr r1, r1, r2
str r1, [r0]
ldr r0, = GPBCON ; GPB10: Output
ldr r1, [r0]
ldr r2, = 0x0fffff
and r1, r1, r2
ldr r2, = (1<<20)
orr r1, r1, r2
str r1, [r0]
ldr r0, = GPBDAT ; Latch disable
ldr r1, [r0]
ldr r2, = (1<<8)
orr r1, r1, r2
str r1, [r0]
]
; end for 533Mhz code
ldr r0, = INTMSK
ldr r1, = ~BIT_BAT_FLT ; all interrupt disable, nBATT_FLT =enabled
str r1, [r0]
ldr r0, = INTSUBMSK
ldr r1, = 0x7ff ;all sub interrupt disable
str r1, [r0]
ldr r0, = INTMOD
ldr r1, = BIT_BAT_FLT ; set all interrupt as IRQ, BAT_FLT = FIQ
str r1, [r0]
ldr r1, =MISCCR ; MISCCR's Bit [22:20] -> 100
ldr r0, [r1]
bic r0, r0, #(7 << 20)
orr r0, r0, #(4 << 20)
str r0, [r1]
bl ARMClearUTLB
bl ARMFlushICache
ldr r0, = (DCACHE_LINES_PER_SET - 1)
ldr r1, = (DCACHE_NUM_SETS - 1)
ldr r2, = DCACHE_SET_INDEX_BIT
ldr r3, = DCACHE_LINE_SIZE
bl ARMFlushDCache
nop
nop
nop
ldr r0, = GPFCON
ldr r1, = 0x55aa
str r1, [r0]
ldr r0, = WTCON ; watch dog disable
ldr r1, = 0x0
str r1, [r0]
[ {TRUE}
ldr r0, = CLKDIVN
ldr r1, = CLKDIVVAL ; 0x0 = 1:1:1 , 0x1 = 1:1:2, use CLKDIVVAL instead of 7
; 0x2 = 1:2:2 , 0x3 = 1:2:4, 0x4 = 1:4:4, 0x5 = 1:4:8, 0x6 = 1:3:3, 0x7 = 1:3:6
str r1, [r0]
ands r1, r1, #0xe ; Make AsyncBusMode
beq %F1
mrc p15, 0, r0, c1, c0, 0
orr r0, r0, #R1_nF:OR:R1_iA
mcr p15, 0, r0, c1, c0, 0
1
ldr r0, = LOCKTIME ; To reduce PLL lock time, adjust the LOCKTIME register.
ldr r1, = 0xffffff
str r1, [r0]
ldr r0, = UPLLCON ; Fin=12MHz, Fout=48MHz
[ FIN = 12
ldr r1, = ((0x38 << 12) + (0x2 << 4) + 0x2)
|
ldr r1, = ((60 << 12) + (4 << 4) + 0x2)
]
str r1, [r0]
nop ; Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.
nop
nop
nop
nop
nop
nop
ldr r0, = CAMDIVN
ldr r1, = 0
str r1, [r0]
ldr r0, = MPLLCON ; Configure MPLL ; Fin=12MHz, Fout=50MHz
ldr r1, = PLLVAL
str r1, [r0]
]
mov r0, #0x2000
1
subs r0, r0, #1
bne %B1
; :::::::::::::::::::::::::::::::::::::::::::::
; Add for Power Management
; - - - - - - - - - - - - - - - - - - - - - - -
ldr r1, =GSTATUS2 ; Determine Booting Mode
ldr r10, [r1]
tst r10, #0x2 ; Power-Off reset Check
beq %F2 ; if not wakeup from PowerOffmode
; goto Watchdog reset test.
b %F3 ; if wakeup from PowerOff mode
; goto Power-up code.
; Watchdog reset
2
tst r10, #0x4 ; In case of the wake-up from Watchdog reset,
; go to SDRAM start address(0x3020_0000)
b %F4 ; If not wakeup from Watchdog reset,
beq %F4 ; If not wakeup from Watchdog reset,
; goto Normal Mode.
mov r0, #4
str r0, [r1] ; Clear the GSTATUS2. Because same code is located in memory address.
; Set memory control registers
add r0, pc, #SMRDATA - (. + 8)
ldr r1, = BWSCON ; BWSCON Address
add r2, r0, #52 ; End address of SMRDATA
loop0
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne loop0
mov r1, #256
loop1
subs r1, r1, #1 ; wait until the SelfRefresh is released.
bne loop1
ldr r2, =0x201000 ; offset into the RAM
add r2, r2, #0x30000000 ; add physical base
mov pc, r2 ; & jump to StartUp address
b .
; Case of Power-off reset
3
ldr r1, =MISCCR ; MISCCR's Bit 17, 18, 19 -> 0
ldr r0, [r1]
bic r0, r0, #(3 << 17)
str r0, [r1]
; - - - - - - - - - - - - - - - - - - - - - - -
; Add for Power Management
; :::::::::::::::::::::::::::::::::::::::::::::
4
add r0, pc, #SMRDATA - (. + 8)
ldr r1, = BWSCON ; BWSCON Address
add r2, r0, #52 ; End address of SMRDATA
1
ldr r3, [r0], #4
str r3, [r1], #4
cmp r2, r0
bne %B1
; :::::::::::::::::::::::::::::::::::::::::::::
; Add for Power Management
; - - - - - - - - - - - - - - - - - - - - - - -
tst r10, #0x2 ; Power-Off reset check
beq BringUpWinCE ; Normal Mode Booting
; Recover Process : Starting Point
ldr r1, =GSTATUS2 ; Determine Booting Mode
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