?? power.c
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//Setting: IN IN IN IN IN IN OUT RXD0 TXD0 OUT IN
//Binary : 00, 00 00, 00 00, 00 01, 10 10, 01 00
//PU_OFF : 0 0 0, 1-ext 1-ext 1-ext 1, 1-ext 1 1 1-ext
#if 1
s2440IOP->rGPHDAT = 0x0|(1<<6)|(1<<1)|(1<<4);
s2440IOP->rGPHCON = 0x0001a4; //0x0011a4->0x0001a4 reduces 12uA why -> MAX3232C may sink 12uA.
#else
//rGPHDAT = 0x0|(1<<6)|(1<<1)|(1<<4);
//rGPHCON = 0x0011a4;
s2440IOP->rGPHDAT = 0x0|(0<<6)|(1<<1)|(1<<4); //(1<<6)->(0<<6) reduces 12uA (MAX3232C may sink 12uA.)
s2440IOP->rGPHCON = 0x0011a4;
#endif
s2440IOP->rGPHUP = 0x0ff; // The pull up function is disabled GPH[10:0]
//PORT J GROUP
//Ports : GPJ12 GPJ11 GPJ10 GPJ9 GPJ8 GPJ7 GPJ6 GPJ5 GPJ4 GPJ3 GPJ2 GPJ1 GPJ0
//Signal : CAMRESET CAMCLKOUT CAMHREF CAMVS CAMPCLKIN CAMD7 CAMD6 CAMD5 CAMD4 CAMD3 CAMD2 CAMD1 CAMD0
//Setting: Out Out Out Out Out Out Out Out Out Out Out Out Out
//Binary : 01 01 01 01 01 01 01 01 01 01 01 01 01
//PU_OFF : 0 0 1 1 1 1 1 1 1 1 1 1 1
//---------------------------------------------------------------------------------------
s2440IOP->rGPJCON = 0x02aaaaaa;
s2440IOP->rGPJUP = 0x1fff; // The pull up function is disabled GPH[10:0]
//External interrupt will be falling edge triggered.
// s2440IOP->rEXTINT0 = 0x22222222; // EINT[7:0]
s2440IOP->rEXTINT0 = 0x22222224; // EINT[7:0] // charlie. button glich
s2440IOP->rEXTINT1 = 0x22222222; // EINT[15:8]
s2440IOP->rEXTINT2 = 0x22222022; // EINT[23:16]
}
void ConfigMiscReg(void)
{
volatile IOPreg *s2440IOP = (IOPreg *)IOP_BASE;
volatile ADCreg *s2440ADC = (ADCreg *)ADC_BASE;
volatile RTCreg *s2440RTC = (RTCreg *)RTC_BASE;
s2440RTC->rRTCCON=0x0; // R/W disable, 1/32768, Normal(merge), No reset
s2440ADC->rADCCON|=(1<<2); // ADC StanbyMode
s2440IOP->rMISCCR|=(1<<12); //USB port0 = suspend
s2440IOP->rMISCCR|=(1<<13); //USB port1 = suspend
s2440IOP->rMISCCR|=(1<<2); //Previous state at STOP(?) mode (???)
//D[31:0] pull-up off. The data bus will not be float by the external bus holder.
//If the pull-up resitsers are turned on,
//there will be the leakage current through the pull-up resister
s2440IOP->rMISCCR=s2440IOP->rMISCCR|(3<<0);
// In the evaluation board, Even though in sleep mode, the devices are all supplied the power.
s2440IOP->rMSLCON = (0<<11)|(0<<10)|(0<<9)|(0<<8)|(0<<7)|(0<<6)|(0<<5)|(0<<4)|(0<<3)|(0<<2)|(0<<1)|(0<<0);
s2440IOP->rDSC0 = (1<<31)|(3<<8)|(3<<0);
s2440IOP->rDSC1 = (3<<28)|(3<<26)|(3<24)|(3<<22)|(3<<20)|(3<<18);
}
PRIVATE void
CPULCDOff(void)
{
volatile IOPreg *s2440IOP = (IOPreg *)IOP_BASE;
volatile LCDreg *s2440LCD = (LCDreg *)LCD_BASE;
s2440IOP->rGPGDAT &= ~(1 << 4);
s2440LCD->rLCDCON1 = 0;
s2440LCD->rLCDCON2 = 0;
s2440LCD->rLCDCON3 = 0;
s2440LCD->rLCDCON4 = 0;
s2440LCD->rLCDCON5 = 0;
s2440LCD->rLCDSADDR1 = 0;
s2440LCD->rLCDSADDR2 = 0;
s2440LCD->rLCDSADDR3 = 0;
s2440LCD->rTCONSEL = 0;
s2440LCD->rTPAL = 0;
}
PRIVATE void
CPUClearCS8900(void)
{
USHORT temp;
// RETAILMSG(1,(TEXT("CPUClearCS8900 Enter\r\n")));
do
{
temp = *((volatile USHORT *)(CS8900DBG_IOBASE + 8));
} while (temp != 0);
// RETAILMSG(1,(TEXT("CPUClearCS8900 Out\r\n")));
}
void NANDInit(void)
{
#define NFCONF_INIT 0xF850
// HCLK=133Mhz
#define TACLS 0
#define TWRPH0 6
#define TWRPH1 0
volatile NANDreg *s2440NAND = (NANDreg *)NAND_BASE;
volatile CLKPWRreg *s2440CLK = (CLKPWRreg *)CLKPWR_BASE;
// Enable the clock to NAND controller
s2440CLK->rCLKCON |= (1<<4);
// Now we need enable the NAND Flash controller
// s2440NAND->rNFCONF = NFCONF_INIT;
s2440NAND->rNFCONF = (TACLS<<12)|(TWRPH0<<8)|(TWRPH1<<4)|(0<<0);
s2440NAND->rNFCONT = (0<<13)|(0<<12)|(0<<10)|(0<<9)|(0<<8)|(0<<6)|(0<<5)|(1<<4)|(1<<1)|(1<<0);
s2440NAND->rNFSTAT = 0;
}
VOID OEMPowerOff(void)
{
volatile IOPreg *s2440IOP = (IOPreg *)IOP_BASE;
volatile INTreg *s2440INT = (INTreg *)INT_BASE;
volatile LCDreg *s2440LCD = (LCDreg *)LCD_BASE;
volatile CLKPWRreg * s2440CLKPW = (CLKPWRreg *)CLKPWR_BASE;
// RETAILMSG(1,(TEXT("++ Enter OEMPOWER.\r\n")));
// Allow KITL to save its state
// if(gpfnKitlPowerHandler) {
// gpfnKitlPowerHandler(TRUE);
// }
/* Save Current Important CPU Regs... */
CPUSaveRegs(CPUBackupRegs);
/* LCD Controller Disable */
CPULCDOff();
/* Stop all GPIO */
ConfigStopGPIO();
/* Set misc register for power off */
ConfigMiscReg();
// s2440CLKPW->rCLKCON = 0xFFFF0;
/* Actual Power-Off Mode Entry */
CPUPowerOff();
// while(1); // for batt_flt debugging
/* Recover Process, Load CPU Regs */
CPULoadRegs(CPUBackupRegs);
/* Interrupt Clear */
s2440IOP->rEINTPEND = s2440IOP->rEINTPEND;
s2440LCD->rLCDSRCPND = s2440LCD->rLCDSRCPND;
s2440LCD->rLCDINTPND = s2440LCD->rLCDINTPND;
s2440INT->rSUBSRCPND = s2440INT->rSUBSRCPND;
// s2440INT->rSRCPND = s2440INT->rSRCPND;
// s2440INT->rINTPND = s2440INT->rINTPND;
NANDInit();
OEMInitDebugSerial();
CPUClearCS8900();
RETAILMSG(1,(TEXT("-- Exit OEMPOWER.\r\n")));
RETAILMSG(1,(TEXT("s2440INT->rSRCPND = 0x%x \r\n"), s2440INT->rSRCPND));
RETAILMSG(1,(TEXT("s2440INT->rINTPND = 0x%x \r\n"), s2440INT->rINTPND));
RETAILMSG(1,(TEXT("s2440INT->rINTMOD = 0x%x \r\n"), s2440INT->rINTMOD));
RETAILMSG(1,(TEXT("s2440INT->rINTMSK = 0x%x \r\n"), s2440INT->rINTMSK));
// while(1); // for batt_flt debugging
// Allow KITL to restore its state
// if(gpfnKitlPowerHandler) {
// gpfnKitlPowerHandler(FALSE);
// }
}
PUBLIC void
OEMEmergencyPowerOff(void)
{
volatile IOPreg *s2440IOP = (IOPreg *)IOP_BASE;
volatile INTreg *s2440INT = (INTreg *)INT_BASE;
volatile LCDreg *s2440LCD = (LCDreg *)LCD_BASE;
volatile CLKPWRreg *s2440CLK = (CLKPWRreg *)CLKPWR_BASE;
/* Save Current Important CPU Regs... */
// CPUSaveRegs(CPUBackupRegs);
s2440IOP->rGPFDAT = ~(0x1 << 5); /* LED Off */
/* LCD Controller Disable */
CPULCDOff();
s2440IOP->rGPFDAT = ~(0x2 << 5); /* LED Off */
/* Stop all GPIO */
ConfigStopGPIO();
s2440IOP->rGPFDAT = ~(0x3 << 5); /* LED Off */
/* Set misc register for power off */
ConfigMiscReg();
s2440IOP->rGPFDAT = ~(0x4 << 5); /* LED Off */
/* Actual Power-Off Mode Entry */
EmergencyCPUPowerOff();
// CPUPowerOff();
}
VOID OEMCPUPowerReset()
{
#if 0
volatile WATCHreg *WTimer = (WATCHreg *) WATCH_BASE;
// Burst refresh with reading all SDRAM area.
Burst_Refresh();
// Mask F bit, I bit.
CLR_IF();
// Set watch dog reset. After this function, watch-dog reset will occure after 500ms.
Watchdog_Set();
// WTimer->rWTCON = ((PCLK/1000000-1) << 8) | /* The prescaler value => 255 + 1 */
// (0x00 << 6) | /* Reserved */
// (0x01 << 5) | /* Timer enable or disable */
// (0x03 << 3) | /* The clock division factor => 16 */
// (0x00 << 2) | /* Disable bit of interrupt */
// (0x00 << 1) | /* Reserved */
// (0x01 << 0); /* Enable the reset function of timer */
//
// while(1);
#endif
// Set memory with self refresh and enable watchdog reset.
CPUPowerReset();
}
#define SDRAM_STARTADDRESS 0x30000000
#define SDRAM_ENDADDRESS 0x33ffffff
void Burst_Refresh(void)
{
// int i;
// for(i=SDRAM_STARTADDRESS; i<SDRAM_ENDADDRESS; i+=8192) // Row addr is 13 bit.
// *(U32 *) i;
}
void CLR_IF()
{
}
//================================================
// Watch-dog timer Interrupt Request Test
//================================================
extern volatile int isWdtInt;
#define WATCHDOG_TIME (128) // [usec], Max=65535*128us.
void Watchdog_Set(void)
{
volatile INTreg *s2440INT = (INTreg *)INT_BASE;
volatile WATCHreg *WTimer = (WATCHreg *) WATCH_BASE;
//t_watchdog = 1 / (PCLK / (Prescaler value + 1 ) / Division_factor)
s2440INT->rINTMSK &= ~(BIT_WDT_AC97); //Watch dog Interrupt service is available
WTimer->rWTCON = ((S2440PCLK/1000000-1) << 8) | /* The prescaler value => 255 + 1 */
(0x00 << 6) | /* Reserved */
(0x00 << 5) | /* Timer enable or disable */
(0x03 << 3) | /* The clock division factor => 16 */
(0x00 << 2) | /* Disable bit of interrupt */
(0x00 << 1) | /* Reserved */
(0x01 << 0); /* Enable the reset function of timer */
WTimer->rWTDAT = 0x1;
WTimer->rWTCNT = 0x1;
// WTimer->rWTCON = ((PCLK/1000000-1)<<8) | (3<<3) | (1); //Prescaler=0x31(49),Clock division 128,Reset enable
// 1*128 usec.
// WTimer->rWTDAT = WATCHDOG_TIME/128;
// WTimer->rWTCNT = WATCHDOG_TIME/128; // (xsec/128us)
}
// End of Power Management
//------------------------------------------------------------------------------
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