/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.
Copyright (c) 2002. Samsung Electronics, co. ltd  All rights reserved.

	[Updates]
	
	2003.03.14 PCMCIA Wakeup fixed. jylee
	
--*/

#include <windows.h>
#include <types.h>
#include <cardserv.h>
#include <sockserv.h>
#include <sockpd.h>
#include <ceddk.h>
//#include <pc.h>
#include <nkintr.h>
#include <oalintr.h>
#include <S2440.h> 
#include <pd6710.h>
#include <drv_glob.h>

extern VOID InitSocketNoCard(UINT uSocket);

//void PD_DataBackup();
void PD_DataRestore();

DWORD gIntrPcmciaState = SYSINTR_PCMCIA_STATE;
DWORD gIntrPcmciaLevel = SYSINTR_PCMCIA_LEVEL;
DWORD g_Irq = 3;        // fixed by S3C2440 development platform

volatile PUCHAR g_PCICIndex;
volatile PUCHAR g_PCICData;
CRITICAL_SECTION g_PCIC_Crit;

volatile IOPreg *v_pIOPRegs;
volatile MEMreg *v_pMEMRegs;
volatile PUCHAR *v_pPCMCIAPort;  

// be written by fwood for wake-up
//volatile IOPreg IOPRegs_bak;
//volatile MEMreg MEMRegs_bak;


// when power up, restore datas
// by shlim
void PD_DataRestore()
{
	UINT8 tmp;

	// Register Restore for wake-up

	// Initialize S3C2440 for PD6710           
	// EINT3(GPF3) is enabled.
	v_pIOPRegs->rGPFCON = (v_pIOPRegs->rGPFCON & ~(0x3<<6)) | (0x2<<6); 
	// EINT3 is PULLUP enabled.
	v_pIOPRegs->rGPFUP = (v_pIOPRegs->rGPFUP & ~(0x1<<3));              

	// EINT8(GPG0) is enabled.
	v_pIOPRegs->rGPGCON = (v_pIOPRegs->rGPGCON & ~(0x3<<0)) | (0x2<<0); 
	// EINT8 is *not* PULLUP enabled.
	//v_pIOPRegs->rGPGUP = (v_pIOPRegs->rGPGUP | (0x1<<0));
	// jylee
	v_pIOPRegs->rGPGUP = (v_pIOPRegs->rGPGUP & ~(0x1<<0)); // pullup enabled

	
	// nGCS2=nUB/nLB(nSBHE),nWAIT,16-bit
	v_pMEMRegs->rBWSCON = (v_pMEMRegs->rBWSCON & ~(0xf<<8)) | (0xd<<8); 

	// BANK2 access timing
	v_pMEMRegs->rBANKCON2 = ((B6710_Tacs<<13)+(B6710_Tcos<<11)+(B6710_Tacc<<8)+(B6710_Tcoh<<6)\
		+(B6710_Tah<<4)+(B6710_Tacp<<2)+(B6710_PMC));

	//v_pIOPRegs->rEINTMASK |= (1<<8);
	v_pIOPRegs->rEXTINT1=(v_pIOPRegs->rEXTINT1 & ~(0xf<<0)) | (0x2<<0); 	// EINT8 : falling edge trigger
	v_pIOPRegs->rEXTINT0=(v_pIOPRegs->rEXTINT0 & ~(0xf<<12)) | (0x2<<12); 	// EINT3 : falling edge trigger
	v_pIOPRegs->rEINTMASK &= ~(1<<8);

	g_PCICIndex = ((volatile PUCHAR)((ULONG)v_pPCMCIAPort+0x3e0));
	g_PCICData  = ((volatile PUCHAR)((ULONG)v_pPCMCIAPort+0x3e1));

	//
	// 0x3E0 is the standard Intel compatible socket controller I/O port.
	//
	PCICIndex(0, REG_CHIP_REVISION);
	tmp = PCICDataRead();
	if ((tmp != 0x83) && (tmp != 0x82)) {
		DEBUGMSG(1,
			(TEXT("PDCardInitServices CHIP_REVISION = 0x%x, expected = 0x83 !!!\r\n"), tmp));
		return ;
	}

	// otput2card_disable, AUTO_POWER, VCC_POWER_OFF,Vpp1=0V
	PCICIndex(0, REG_POWER_CONTROL);
	PCICDataWrite((0<<7) | (1<<5) | (0<<4) | (0<<0));

	// INPACK_ignored,speak_enable,edge_irq_intr,edge_management_intr,nVCC_3_enabled(temp)
	PCICIndex(0, REG_GENERAL_CONTROL);

	// Management int, System int -> edge triggering(PULSE)  
//  PCICDataWrite(MISC1_VCC_33|MISC1_PM_IRQ|MISC1_PS_IRQ|MISC1_SPK_ENABLE);
	// Management int -> edge triggering(PULSE), System int -> LEVEL triggering 
	PCICDataWrite(MISC1_VCC_33|MISC1_PM_IRQ|MISC1_SPK_ENABLE);

	// 25Mhz_bypass,low_power_dynamic,IRQ12=drive_LED
	PCICIndex(0, REG_GLOBAL_CONTROL);
//  PCICDataWrite(MISC2_BFS|MISC2_LOW_POWER_MODE|MISC2_LED_ENABLE);
	PCICDataWrite(MISC2_LOW_POWER_MODE|MISC2_LED_ENABLE);
	
	// before configuring timing register, FIFO should be cleared.
	PCICIndex(0, REG_FIFO_CTRL);
	PCICDataWrite(FIFO_EMPTY_WRITE);    //Flush FIFO

	//default access time is 300ns
	PCICIndex(0, REG_SETUP_TIMING0);
	PCICDataWrite(5);                   //80ns(no spec)
	PCICIndex(0, REG_CMD_TIMING0);
	PCICDataWrite(20);                  //320ns(by spec,25Mhz clock)
	PCICIndex(0, REG_RECOVERY_TIMING0);
	PCICDataWrite(5);                   //80ns(no spec)

	//default access time is 300ns
	PCICIndex(0, REG_SETUP_TIMING1);
	PCICDataWrite(2);                   //80ns(no spec)
	PCICIndex(0, REG_CMD_TIMING1);
	PCICDataWrite(8);                   //320ns(by spec,25Mhz clock)
	PCICIndex(0, REG_RECOVERY_TIMING1);
	PCICDataWrite(2);                   //80ns(no spec)

	PCICIndex(0, REG_CHIP_INFO);
	PCICDataWrite(0);

	PCICIndex(0, REG_CHIP_REVISION);
	tmp = PCICDataRead();
	RETAILMSG(0, (TEXT("PDCardInitServices REG_CHIP_REVISION = 0x%x\r\n"), tmp));

	DEBUGMSG(1, (TEXT("InitSocketNoCard(0) is called\r\n")));	
//	InitSocketNoCard(0);

}


//
// The PCMCIA MDD calls PDCardInitServices to initialize the PDD layer.
//
STATUS
PDCardInitServices(DWORD dwInfo)
{
	UINT8 tmp;
 
	DEBUGMSG (1,(TEXT("++PDCardInitServices\n\r")));

	// Since the single PCMCIA slot can be used for download/KITL, we need to check to see if it's in use supporting a KITL
	// NIC.  If so, we shouldn't proceed with PCMCIA initialization.
	//

	// Allocate PCMCIA buffers.
	v_pIOPRegs = VirtualAlloc(0, sizeof(IOPreg), MEM_RESERVE, PAGE_NOACCESS);
	if (v_pIOPRegs == NULL) 
	{
		DEBUGMSG (1,(TEXT("v_pIOPRegs is not allocated\n\r")));
		goto pcis_fail;
	}
	if (!VirtualCopy((PVOID)v_pIOPRegs, (PVOID)IOP_BASE, sizeof(IOPreg), PAGE_READWRITE|PAGE_NOCACHE)) {
		DEBUGMSG (1,(TEXT("v_pIOPRegs is not mapped\n\r")));
		goto pcis_fail;
	}
	DEBUGMSG (1,(TEXT("v_pIOPRegs is mapped to %x\n\r"), v_pIOPRegs));
	
	v_pMEMRegs = VirtualAlloc(0,sizeof(MEMreg), MEM_RESERVE,PAGE_NOACCESS);
	if(v_pMEMRegs == NULL) 
	{
		DEBUGMSG (1,(TEXT("v_pMEMRegs is not allocated\n\r")));
		goto pcis_fail;
	}
	if(!VirtualCopy((PVOID)v_pMEMRegs,(PVOID)MEMCTRL_BASE,sizeof(MEMreg), PAGE_READWRITE|PAGE_NOCACHE)) {
		DEBUGMSG (1,(TEXT("v_pMEMRegs is not mapped\n\r")));
		goto pcis_fail;
	}    
	DEBUGMSG (1,(TEXT("v_pMEMRegs is mapped to %x\n\r"), v_pMEMRegs));

	v_pPCMCIAPort = VirtualAlloc(0, 0x0400, MEM_RESERVE,PAGE_NOACCESS);
	if(v_pPCMCIAPort == NULL) 
	{
		DEBUGMSG (1,(TEXT("v_pPCMCIAPort is not allocated\n\r")));
		goto pcis_fail;
	}
	if(!VirtualCopy((PVOID)v_pPCMCIAPort,(PVOID)PD6710_IO_BASE_ADDRESS, 0x0400, PAGE_READWRITE|PAGE_NOCACHE)) {
		DEBUGMSG (1,(TEXT("v_pPCMCIAPort is not mapped\n\r")));
		goto pcis_fail;
	}    
	DEBUGMSG (1,(TEXT("v_pPCMCIAPort is mapped to %x\n\r"), v_pPCMCIAPort));
	
	// Initialize S3C2440 for PD6710           
	// EINT3(GPF3) is enabled.
	v_pIOPRegs->rGPFCON = (v_pIOPRegs->rGPFCON & ~(0x3<<6)) | (0x2<<6); 
	// EINT3 is PULLUP enabled.
	v_pIOPRegs->rGPFUP = (v_pIOPRegs->rGPFUP & ~(0x1<<3));              

	// EINT8(GPG0) is enabled.
	v_pIOPRegs->rGPGCON = (v_pIOPRegs->rGPGCON & ~(0x3<<0)) | (0x2<<0); 
	// EINT8 is *not* PULLUP enabled.
	//v_pIOPRegs->rGPGUP = (v_pIOPRegs->rGPGUP | (0x1<<0));
	// jylee
	v_pIOPRegs->rGPGUP = (v_pIOPRegs->rGPGUP & ~(0x1<<0)); // pullup enabled

	
	// nGCS2=nUB/nLB(nSBHE),nWAIT,16-bit
	v_pMEMRegs->rBWSCON = (v_pMEMRegs->rBWSCON & ~(0xf<<8)) | (0xd<<8); 

	// BANK2 access timing
	v_pMEMRegs->rBANKCON2 = ((B6710_Tacs<<13)+(B6710_Tcos<<11)+(B6710_Tacc<<8)+(B6710_Tcoh<<6)\
		+(B6710_Tah<<4)+(B6710_Tacp<<2)+(B6710_PMC));

	
	// jylee 2003.03.19
	//v_pIOPRegs->rEXTINT1=(v_pIOPRegs->rEXTINT1 & ~(0xf<<0)) | (0x7<<0); // both edge trigger
	v_pIOPRegs->rEXTINT1=(v_pIOPRegs->rEXTINT1 & ~(0xf<<0)) | (0x2<<0); 	// EINT8 : falling edge trigger
	v_pIOPRegs->rEXTINT0=(v_pIOPRegs->rEXTINT0 & ~(0xf<<12)) | (0x2<<12); 	// EINT3 : falling edge trigger
		
	g_PCICIndex = ((volatile PUCHAR)((ULONG)v_pPCMCIAPort+0x3e0));
	g_PCICData = ((volatile PUCHAR)((ULONG)v_pPCMCIAPort+0x3e1));

	DEBUGMSG(1,
		(TEXT("PDCardInitServices g_PCICIndex = 0x%x, g_PCICData = 0x%x\r\n"),
		g_PCICIndex, g_PCICData));

	InitializeCriticalSection(&g_PCIC_Crit);
	
	//
	// 0x3E0 is the standard Intel compatible socket controller I/O port.
	//
	PCICIndex(0, REG_CHIP_REVISION);
	tmp = PCICDataRead();
	if ((tmp != 0x83) && (tmp != 0x82)) {