/*---------------------------------------------------------------------------
;  Copyright (C) 2003 CYGNAL INTEGRATED PRODUCTS, INC.
;  All rights reserved.
;
;
;  FILE NAME   : C8051F320.H
;  TARGET MCUs : C8051F320, 'F321, 'F322, 'F323
;  DESCRIPTION : Register/bit definitions for the C8051F32x product family.
;
;  REVISION 1.3
;   -- updated SPI0CN sbit definitions to match datasheet (NSSMD1, NSSMD0)
;  REVISION 1.2
;   -- added SPI0CFG, SPI0CKR, and SPI0DAT (left SPICFG, SPICKR, and SPIDAT as-is)
;  REVISION 1.1
;
;---------------------------------------------------------------------------*/

/*  BYTE Registers  */
sfr P0       = 0x80;    /* PORT 0                                                   */
sfr SP       = 0x81;    /* STACK POINTER                                            */
sfr DPL      = 0x82;    /* DATA POINTER - LOW BYTE                                  */
sfr DPH      = 0x83;    /* DATA POINTER - HIGH BYTE                                 */
sfr PCON     = 0x87;    /* POWER CONTROL                                            */
sfr TCON     = 0x88;    /* TIMER CONTROL                                            */
sfr TMOD     = 0x89;    /* TIMER MODE                                               */
sfr TL0      = 0x8A;    /* TIMER 0 - LOW BYTE                                       */
sfr TL1      = 0x8B;    /* TIMER 1 - LOW BYTE                                       */
sfr TH0      = 0x8C;    /* TIMER 0 - HIGH BYTE                                      */
sfr TH1      = 0x8D;    /* TIMER 1 - HIGH BYTE                                      */
sfr CKCON    = 0x8E;    /* CLOCK CONTROL                                            */
sfr PSCTL    = 0x8F;    /* PROGRAM STORE R/W CONTROL                                */
sfr P1       = 0x90;    /* PORT 1                                                   */
sfr TMR3CN   = 0x91;    /* TIMER 3 CONTROL                                          */
sfr TMR3RLL  = 0x92;    /* TIMER 3 RELOAD LOW                                       */
sfr TMR3RLH  = 0x93;    /* TIMER 3 RELOAD HIGH                                      */
sfr TMR3L    = 0x94;    /* TIMER 3 LOW BYTE                                         */
sfr TMR3H    = 0x95;    /* TIMER 3 HIGH BYTE                                        */
sfr USB0ADR  = 0x96;    /* USB0 ADDRESS PORT                                        */
sfr USB0DAT  = 0x97;    /* USB0 DATA PORT                                           */
sfr SCON0    = 0x98;    /* SERIAL PORT 0 CONTROL                                    */
sfr SBUF0    = 0x99;    /* SERIAL PORT 0 BUFFER                                     */
sfr CPT1CN   = 0x9A;    /* COMPARATOR 1 CONTROL                                     */
sfr CPT0CN   = 0x9B;    /* COMPARATOR 0 CONTROL                                     */
sfr CPT1MD   = 0x9C;    /* COMPARATOR 1 MODE                                        */
sfr CPT0MD   = 0x9D;    /* COMPARATOR 0 MODE                                        */
sfr CPT1MX   = 0x9E;    /* COMPARATOR 1 MUX                                         */
sfr CPT0MX   = 0x9F;    /* COMPARATOR 0 MUX                                         */
sfr P2       = 0xA0;    /* PORT 2                                                   */
sfr SPICFG   = 0xA1;    /* SPI0 CONFIGURATION                                       */
sfr SPI0CFG  = 0xA1;    /* SPI0 CONFIGURATION                                       */
sfr SPICKR   = 0xA2;    /* SPI0 CLOCK CONFIGURATION                                 */
sfr SPI0CKR  = 0xA2;    /* SPI0 CLOCK CONFIGURATION                                 */
sfr SPIDAT   = 0xA3;    /* SPI0 DATA                                                */
sfr SPI0DAT  = 0xA3;    /* SPI0 DATA                                                */
sfr P0MDOUT  = 0xA4;    /* PORT 0 OUTPUT MODE                                       */
sfr P1MDOUT  = 0xA5;    /* PORT 1 OUTPUT MODE                                       */
sfr P2MDOUT  = 0xA6;    /* PORT 2 OUTPUT MODE                                       */
sfr P3MDOUT  = 0xA7;    /* PORT 3 OUTPUT MODE                                       */
sfr IE       = 0xA8;    /* INTERRUPT ENABLE                                         */
sfr CLKSEL   = 0xA9;    /* CLOCK SOURCE SELECT                                      */
sfr P3       = 0xB0;    /* PORT 3                                                   */
sfr OSCXCN   = 0xB1;    /* EXTERNAL OSCILLATOR CONTROL                              */
sfr OSCICN   = 0xB2;    /* INTERNAL OSCILLATOR CONTROL                              */
sfr OSCICL   = 0xB3;    /* INTERNAL OSCILLATOR CALIBRATION                          */
sfr FLSCL    = 0xB6;    /* FLASH SCALE                                              */
sfr FLKEY    = 0xB7;    /* FLASH LOCK & KEY                                         */
sfr IP       = 0xB8;    /* INTERRUPT PRIORITY                                       */
sfr CLKMUL   = 0xB9;    /* CLOCK MULTIPLIER CONTROL                                 */
sfr AMX0N    = 0xBA;    /* ADC0 MUX NEGATIVE CHANNEL SELECTION                      */
sfr AMX0P    = 0xBB;    /* ADC0 MUX POSITIVE CHANNEL SELECTION                      */
sfr ADC0CF   = 0xBC;    /* ADC0 CONFIGURATION                                       */
sfr ADC0L    = 0xBD;    /* ADC0 DATA LOW                                            */
sfr ADC0H    = 0xBE;    /* ADC0 DATA HIGH                                           */
sfr SMB0CN   = 0xC0;    /* SMBUS CONTROL                                            */
sfr SMB0CF   = 0xC1;    /* SMBUS CONFIGURATION                                      */
sfr SMB0DAT  = 0xC2;    /* SMBUS DATA                                               */
sfr ADC0GTL  = 0xC3;    /* ADC0 GREATER-THAN LOW                                    */
sfr ADC0GTH  = 0xC4;    /* ADC0 GREATER-THAN HIGH                                   */
sfr ADC0LTL  = 0xC5;    /* ADC0 LESS-THAN LOW                                       */
sfr ADC0LTH  = 0xC6;    /* ADC0 LESS-THAN HIGH                                      */
sfr TMR2CN   = 0xC8;    /* TIMER 2 CONTROL                                          */
sfr REG0CN   = 0xC9;    /* REGULATOR CONTROl                                        */
sfr TMR2RLL  = 0xCA;    /* TIMER 2 RELOAD LOW                                       */
sfr TMR2RLH  = 0xCB;    /* TIMER 2 RELOAD HIGH                                      */
sfr TMR2L    = 0xCC;    /* TIMER 2 LOW BYTE                                         */
sfr TMR2H    = 0xCD;    /* TIMER 2 HIGH BYTE                                        */
sfr PSW      = 0xD0;    /* PROGRAM STATUS WORD                                      */
sfr REF0CN   = 0xD1;    /* VOLTAGE REFERENCE 0 CONTROL                              */
sfr P0SKIP   = 0xD4;    /* PORT 0 CROSSBAR SKIP                                     */
sfr P1SKIP   = 0xD5;    /* PORT 1 CROSSBAR SKIP                                     */
sfr P2SKIP   = 0xD6;    /* PORT 2 CROSSBAR SKIP                                     */
sfr USB0XCN  = 0xD7;    /* USB0 TRANCEIVER CONTROL                                  */
sfr PCA0CN   = 0xD8;    /* PCA0 CONTROL                                             */
sfr PCA0MD   = 0xD9;    /* PCA0 MODE                                                */
sfr PCA0CPM0 = 0xDA;    /* PCA0 MODULE 0 MODE                                       */
sfr PCA0CPM1 = 0xDB;    /* PCA0 MODULE 1 MODE                                       */
sfr PCA0CPM2 = 0xDC;    /* PCA0 MODULE 2 MODE                                       */
sfr PCA0CPM3 = 0xDD;    /* PCA0 MODULE 3 MODE                                       */
sfr PCA0CPM4 = 0xDE;    /* PCA0 MODULE 4 MODE                                       */
sfr ACC      = 0xE0;    /* ACCUMULATOR                                              */
sfr XBR0     = 0xE1;    /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0                */
sfr XBR1     = 0xE2;    /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1                */
sfr IT01CF   = 0xE4;    /* INT0/INT1 CONFIGURATION                                  */
sfr EIE1     = 0xE6;    /* EXTENDED INTERRUPT ENABLE 1                              */
sfr ADC0CN   = 0xE8;    /* ADC 0 CONTROL                                            */
sfr PCA0CPL1 = 0xE9;    /* PCA0 MODULE 1 CAPTURE/COMPARE REGISTER LOW BYTE          */
sfr PCA0CPH1 = 0xEA;    /* PCA0 MODULE 1 CAPTURE/COMPARE REGISTER HIGH BYTE         */
sfr PCA0CPL2 = 0xEB;    /* PCA0 MODULE 2 CAPTURE/COMPARE REGISTER LOW BYTE          */
sfr PCA0CPH2 = 0xEC;    /* PCA0 MODULE 2 CAPTURE/COMPARE REGISTER HIGH BYTE         */
sfr PCA0CPL3 = 0xED;    /* PCA0 MODULE 3 CAPTURE/COMPARE REGISTER LOW BYTE          */
sfr PCA0CPH3 = 0xEE;    /* PCA0 MODULE 3 CAPTURE/COMPARE REGISTER HIGH BYTE         */