#----------------------------------------------------------
# Synopsys FPGA Compiler II simulation script verilog.fc2 
# for the book: Digital Signal Processing with FPGAs
# Author-EMAIL: Uwe.Meyer-Baese@ieee.org
#----------------------------------------------------------
# Usage: fc2_shell -f verilog.fc2
#----------------------------------------------------------
create_project -dir . fc2
#*** Chapter 1 entitys:
set ch1 "example fun_text"
#*** Chapter 2 components: 
set ch2 "csa7 csa7cin add_ff8 add_ff8cin"
#*** Chapter 2 entitys: 
set ch2e "add_1p add_2p add_3p mul_ser cordic"
#*** Chapter 3 components:
set ch3 "case3 case5p case3s"
#*** Chapter 3 entitys: 
set ch3e "fir_gen fir_srg dafsm darom dasign dapara"
#*** Chapter 4 entitys: 
set ch4 "iir iir_pipe iir_par"
#*** Chapter 5 entitys: 
set ch5 "cic3r32 cic3s32 db4poly db4latti"
#*** Chapter 6 entitys:
set ch6 "rader7 ccmul bfproc"
#*** Chapter 7 entitys:
set ch7 "lfsr lfsr6s3 ammod"

#*** Make a single list of all VHDL files
set files "$ch1 $ch2 $ch2e $ch3 $ch3e $ch4 $ch5 $ch6 $ch7" 

#*** Compile all files in the list and report results
foreach current $files {
  add_file $current.v
  analyze_file
  create_chip -progress -name $current  \
     -target FLEX10K -device EPF10K20RC240 -speed -4 \
     -frequency 30 $current
  current_chip $current
  optimize_chip -name $current-opt
  report_chip > $current.rpt
  export_chip -dir fc2
}

#----------------------------------------------------------
#*** You may select similar target devices from other 
#*** vendors. Use the following options for the 
#*** "create_chip" command:
# Xilinx:   -target XC4000E -device 4013EPG223 -speed -4 
# Vantis    -target VF1 -device VF1020AMYTC -speed 1
# Actel:    -target A1400 -device  A14100BPRQ208 -speed STD
# QuickLogic: 
#           -target QLOGIC -device  QL3040-PQ240 -speed -4
#----------------------------------------------------------

quit