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-- MTI Verilog port check script for the book
-- Digital Signal Processing with FPGAs
-- Author-EMAIL: Uwe.Meyer-Baese@ieee.org
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echo Check chapter 1 entitys: example and fun_text
vsim lpm.example
vsim -pli convert_hex2ver.sl lpm.fun_text

echo Check chapter 2 components: csa7, csa7cin, add_ff8, and add_ff8cin 
vsim lpm.csa7 
vsim lpm.csa7cin 
vsim lpm.add_ff8 
vsim lpm.add_ff8cin

echo Check chapter 2 entitys: add_1p, add_2p, add_3p, mul_ser, and cordic
vsim lpm.add_1p 
vsim lpm.add_2p 
vsim lpm.add_3p 
vsim lpm.mul_ser 
vsim lpm.cordic 

echo Check chapter 3 components: case3, case5p, and case3s
vsim lpm.case3 
vsim lpm.case5p 
vsim lpm.case3s
echo Check chapter 3 entitys: fir_gen, fir_srg, dafsm, darom, dasign, and dapara
vsim lpm.fir_gen 
vsim lpm.fir_srg 
vsim lpm.dafsm 
vsim -pli convert_hex2ver.sl lpm.darom 
vsim lpm.dasign 
vsim lpm.dapara 

echo Check chapter 4 entitys: iir, iir_pipe, and iir_par 
vsim lpm.iir 
vsim lpm.iir_pipe 
vsim lpm.iir_par  

echo Check chapter 5 entitys: cic3r32, cic3s32, db4poly, and db4latti 
vsim lpm.cic3r32 
vsim lpm.cic3s32 
vsim lpm.db4poly 
vsim lpm.db4latti  

echo Check chapter 6 entitys: rader7, ccmul, and bfproc 
vsim lpm.rader7 
vsim lpm.ccmul
vsim lpm.bfproc  

echo Check chapter 7 entitys: lfsr, lfsr_step3 and ammod 
vsim lpm.lfsr 
vsim lpm.lfsr6s3 
vsim lpm.ammod