?? 220model.vhd
字號:
end process;
RESULT <= IRESULT;
end LPM_SYN;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use work.LPM_COMPONENTS.all;
entity LPM_ADD_SUB_SIGNED is
generic (LPM_WIDTH : positive;
LPM_DIRECTION : string := "UNUSED";
LPM_PIPELINE : integer := 0;
LPM_TYPE : string := "LPM_ADD_SUB";
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTH downto 1);
DATAB : in std_logic_vector(LPM_WIDTH downto 1);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
CIN : in std_logic := '0';
ADD_SUB : in std_logic := '1';
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
COUT : out std_logic;
OVERFLOW : out std_logic);
end LPM_ADD_SUB_SIGNED;
architecture LPM_SYN of LPM_ADD_SUB_SIGNED is
signal A, B : std_logic_vector(LPM_WIDTH downto 0);
type t_resulttmp IS ARRAY (0 to LPM_PIPELINE) of std_logic_vector(LPM_WIDTH downto 0);
begin
A <= (DATAA(LPM_WIDTH) & DATAA);
B <= (DATAB(LPM_WIDTH) & DATAB);
process(ACLR, CLOCK, A, B, CIN, ADD_SUB)
variable resulttmp : t_resulttmp;
variable couttmp : std_logic_vector(0 to LPM_PIPELINE);
variable overflowtmp : std_logic_vector(0 to LPM_PIPELINE);
begin
if LPM_PIPELINE >= 0 then
if LPM_DIRECTION = "ADD" or
(LPM_DIRECTION /= "SUB" and ADD_SUB = '1') then
resulttmp(LPM_PIPELINE) := A + B + CIN;
couttmp(LPM_PIPELINE) := resulttmp(LPM_PIPELINE)(LPM_WIDTH)
xor DATAA(LPM_WIDTH)
xor DATAB(LPM_WIDTH);
else
resulttmp(LPM_PIPELINE) := A - B + CIN - 1;
couttmp(LPM_PIPELINE) := not resulttmp(LPM_PIPELINE)(LPM_WIDTH)
xor DATAA(LPM_WIDTH)
xor DATAB(LPM_WIDTH);
end if;
if (resulttmp(LPM_PIPELINE) > (2 ** (LPM_WIDTH-1)) -1) or
(resulttmp(LPM_PIPELINE) < -2 ** (LPM_WIDTH-1)) then
overflowtmp(LPM_PIPELINE) := '1';
else
overflowtmp(LPM_PIPELINE) := '0';
end if;
if LPM_PIPELINE > 0 then
if ACLR = '1' then
overflowtmp := (OTHERS => '0');
couttmp := (OTHERS => '0');
for i in 0 to LPM_PIPELINE loop
resulttmp(i) := (OTHERS => '0');
end loop;
elsif CLOCK'event and CLOCK = '1' and CLKEN = '1' then
overflowtmp(0 to LPM_PIPELINE - 1) := overflowtmp(1 to LPM_PIPELINE);
couttmp(0 to LPM_PIPELINE - 1) := couttmp(1 to LPM_PIPELINE);
resulttmp(0 to LPM_PIPELINE - 1) := resulttmp(1 to LPM_PIPELINE);
end if;
end if;
COUT <= couttmp(0);
OVERFLOW <= overflowtmp(0);
RESULT <= resulttmp(0)(LPM_WIDTH-1 downto 0);
end if;
end process;
end LPM_SYN;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
entity LPM_ADD_SUB_UNSIGNED is
generic (LPM_WIDTH : positive;
LPM_DIRECTION : string := "UNUSED";
LPM_PIPELINE : integer := 0;
LPM_TYPE : string := "LPM_ADD_SUB";
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
CIN : in std_logic := '0';
ADD_SUB : in std_logic := '1';
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
COUT : out std_logic;
OVERFLOW : out std_logic);
end LPM_ADD_SUB_UNSIGNED;
architecture LPM_SYN of LPM_ADD_SUB_UNSIGNED is
signal A, B : std_logic_vector(LPM_WIDTH downto 0);
type t_resulttmp IS ARRAY (0 to LPM_PIPELINE) of std_logic_vector(LPM_WIDTH downto 0);
begin
A <= ('0' & DATAA);
B <= ('0' & DATAB);
process(ACLR, CLOCK, A, B, CIN, ADD_SUB)
variable resulttmp : t_resulttmp;
variable couttmp : std_logic_vector(0 to LPM_PIPELINE);
variable overflowtmp : std_logic_vector(0 to LPM_PIPELINE);
begin
if LPM_PIPELINE >= 0 then
if LPM_DIRECTION = "ADD" or
(LPM_DIRECTION /= "SUB" and ADD_SUB = '1') then
resulttmp(LPM_PIPELINE) := A + B + CIN;
couttmp(LPM_PIPELINE) := resulttmp(LPM_PIPELINE)(LPM_WIDTH);
else
resulttmp(LPM_PIPELINE) := A - B + CIN - 1;
couttmp(LPM_PIPELINE) := not resulttmp(LPM_PIPELINE)(LPM_WIDTH);
end if;
overflowtmp(LPM_PIPELINE) := resulttmp(LPM_PIPELINE)(LPM_WIDTH);
if LPM_PIPELINE > 0 then
if ACLR = '1' then
overflowtmp := (OTHERS => '0');
couttmp := (OTHERS => '0');
for i in 0 to LPM_PIPELINE loop
resulttmp(i) := (OTHERS => '0');
end loop;
elsif CLOCK'event and CLOCK = '1' and CLKEN = '1' then
overflowtmp(0 to LPM_PIPELINE - 1) := overflowtmp(1 to LPM_PIPELINE);
couttmp(0 to LPM_PIPELINE - 1) := couttmp(1 to LPM_PIPELINE);
resulttmp(0 to LPM_PIPELINE - 1) := resulttmp(1 to LPM_PIPELINE);
end if;
end if;
COUT <= couttmp(0);
OVERFLOW <= overflowtmp(0);
RESULT <= resulttmp(0)(LPM_WIDTH-1 downto 0);
end if;
end process;
end LPM_SYN;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
entity LPM_ADD_SUB is
generic (LPM_WIDTH : positive;
LPM_DIRECTION : string := "UNUSED";
LPM_REPRESENTATION: string := "SIGNED";
LPM_PIPELINE : integer := 0;
LPM_TYPE : string := "LPM_ADD_SUB";
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
CIN : in std_logic := '0';
ADD_SUB : in std_logic := '1';
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
COUT : out std_logic;
OVERFLOW : out std_logic);
end LPM_ADD_SUB;
architecture LPM_SYN of LPM_ADD_SUB is
component LPM_ADD_SUB_SIGNED
generic (LPM_WIDTH : positive;
LPM_DIRECTION : string := "UNUSED";
LPM_PIPELINE : integer := 0;
LPM_TYPE : string := "LPM_ADD_SUB";
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTH downto 1);
DATAB : in std_logic_vector(LPM_WIDTH downto 1);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
CIN : in std_logic := '0';
ADD_SUB : in std_logic := '1';
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
COUT : out std_logic;
OVERFLOW : out std_logic);
end component;
component LPM_ADD_SUB_UNSIGNED
generic (LPM_WIDTH : positive;
LPM_DIRECTION : string := "UNUSED";
LPM_PIPELINE : integer := 0;
LPM_TYPE : string := "LPM_ADD_SUB";
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
CIN : in std_logic := '0';
ADD_SUB : in std_logic := '1';
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
COUT : out std_logic;
OVERFLOW : out std_logic);
end component;
begin
L1: if LPM_REPRESENTATION = "UNSIGNED" generate
U: LPM_ADD_SUB_UNSIGNED
generic map (LPM_WIDTH => LPM_WIDTH, LPM_DIRECTION => LPM_DIRECTION,
LPM_PIPELINE => LPM_PIPELINE, LPM_TYPE => LPM_TYPE,
LPM_HINT => LPM_HINT)
port map (DATAA => DATAA, DATAB => DATAB, ACLR => ACLR, CLOCK => CLOCK,
CIN => CIN, ADD_SUB => ADD_SUB, RESULT => RESULT, COUT => COUT,
OVERFLOW => OVERFLOW, CLKEN => CLKEN);
end generate;
L2: if LPM_REPRESENTATION = "SIGNED" generate
V: LPM_ADD_SUB_SIGNED
generic map (LPM_WIDTH => LPM_WIDTH, LPM_DIRECTION => LPM_DIRECTION,
LPM_PIPELINE => LPM_PIPELINE, LPM_TYPE => LPM_TYPE,
LPM_HINT => LPM_HINT)
port map (DATAA => DATAA, DATAB => DATAB, ACLR => ACLR, CLOCK => CLOCK,
CIN => CIN, ADD_SUB => ADD_SUB, RESULT => RESULT, COUT => COUT,
OVERFLOW => OVERFLOW, CLKEN => CLKEN);
end generate;
end LPM_SYN;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use work.LPM_COMPONENTS.all;
entity LPM_COMPARE_SIGNED is
generic (LPM_WIDTH : positive;
LPM_PIPELINE : integer := 0;
LPM_TYPE: string := "LPM_COMPARE";
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
AGB : out std_logic;
AGEB : out std_logic;
AEB : out std_logic;
ANEB : out std_logic;
ALB : out std_logic;
ALEB : out std_logic);
end LPM_COMPARE_SIGNED;
architecture LPM_SYN of LPM_COMPARE_SIGNED is
begin
process(ACLR, CLOCK, DATAA, DATAB)
variable agbtmp : std_logic_vector (0 to LPM_PIPELINE);
variable agebtmp : std_logic_vector (0 to LPM_PIPELINE);
variable aebtmp : std_logic_vector (0 to LPM_PIPELINE);
variable anebtmp : std_logic_vector (0 to LPM_PIPELINE);
variable albtmp : std_logic_vector (0 to LPM_PIPELINE);
variable alebtmp : std_logic_vector (0 to LPM_PIPELINE);
begin
if LPM_PIPELINE >= 0 then
if DATAA > DATAB then
agbtmp(LPM_PIPELINE) := '1';
agebtmp(LPM_PIPELINE) := '1';
anebtmp(LPM_PIPELINE) := '1';
aebtmp(LPM_PIPELINE) := '0';
albtmp(LPM_PIPELINE) := '0';
alebtmp(LPM_PIPELINE) := '0';
elsif DATAA = DATAB then
agbtmp(LPM_PIPELINE) := '0';
agebtmp(LPM_PIPELINE) := '1';
anebtmp(LPM_PIPELINE) := '0';
aebtmp(LPM_PIPELINE) := '1';
albtmp(LPM_PIPELINE) := '0';
alebtmp(LPM_PIPELINE) := '1';
else
agbtmp(LPM_PIPELINE) := '0';
agebtmp(LPM_PIPELINE) := '0';
anebtmp(LPM_PIPELINE) := '1';
aebtmp(LPM_PIPELINE) := '0';
albtmp(LPM_PIPELINE) := '1';
alebtmp(LPM_PIPELINE) := '1';
end if;
if LPM_PIPELINE > 0 then
if ACLR = '1' then
for i in 0 to LPM_PIPELINE loop
agbtmp(i) := '0';
agebtmp(i) := '0';
anebtmp(i) := '0';
aebtmp(i) := '0';
albtmp(i) := '0';
alebtmp(i) := '0';
end loop;
elsif CLOCK'event and CLOCK = '1' and CLKEN = '1' then
agbtmp(0 to LPM_PIPELINE-1) := agbtmp(1 to LPM_PIPELINE);
agebtmp(0 to LPM_PIPELINE-1) := agebtmp(1 to LPM_PIPELINE) ;
anebtmp(0 to LPM_PIPELINE-1) := anebtmp(1 to LPM_PIPELINE);
aebtmp(0 to LPM_PIPELINE-1) := aebtmp(1 to LPM_PIPELINE);
albtmp(0 to LPM_PIPELINE-1) := albtmp(1 to LPM_PIPELINE);
alebtmp(0 to LPM_PIPELINE-1) := alebtmp(1 to LPM_PIPELINE);
end if;
end if;
end if;
AGB <= agbtmp(0);
AGEB <= agebtmp(0);
ANEB <= anebtmp(0);
AEB <= aebtmp(0);
ALB <= albtmp(0);
ALEB <= alebtmp(0);
end process;
end LPM_SYN;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
entity LPM_COMPARE_UNSIGNED is
generic (LPM_WIDTH : positive;
LPM_PIPELINE : integer := 0;
LPM_TYPE: string := "LPM_COMPARE";
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
AGB : out std_logic;
AGEB : out std_logic;
AEB : out std_logic;
ANEB : out std_logic;
ALB : out std_logic;
ALEB : out std_logic);
end LPM_COMPARE_UNSIGNED;
architecture LPM_SYN of LPM_COMPARE_UNSIGNED is
begin
process(ACLR, CLOCK, DATAA, DATAB)
variable agbtmp : std_logic_vector (0 to LPM_PIPELINE);
variable agebtmp : std_logic_vector (0 to LPM_PIPELINE);
variable aebtmp : std_logic_vector (0 to LPM_PIPELINE);
variable anebtmp : std_logic_vector (0 to LPM_PIPELINE);
variable albtmp : std_logic_vector (0 to LPM_PIPELINE);
variable alebtmp : std_logic_vector (0 to LPM_PIPELINE);
begin
if LPM_PIPELINE >= 0 then
if DATAA > DATAB then
agbtmp(LPM_PIPELINE) := '1';
agebtmp(LPM_PIPELINE) := '1';
anebtmp(LPM_PIPELINE) := '1';
aebtmp(LPM_PIPELINE) := '0';
albtmp(LPM_PIPELINE) := '0';
alebtmp(LPM_PIPELINE) := '0';
elsif DATAA = DATAB then
agbtmp(LPM_PIPELINE) := '0';
agebtmp(LPM_PIPELINE) := '1';
anebtmp(LPM_PIPELINE) := '0';
aebtmp(LPM_PIPELINE) := '1';
albtmp(LPM_PIPELINE) := '0';
alebtmp(LPM_PIPELINE) := '1';
else
agbtmp(LPM_PIPELINE) := '0';
agebtmp(LPM_PIPELINE) := '0';
anebtmp(LPM_PIPELINE) := '1';
aebtmp(LPM_PIPELINE) := '0';
albtmp(LPM_PIPELINE) := '1';
alebtmp(LPM_PIPELINE) := '1';
end if;
if LPM_PIPELINE > 0 then
if ACLR = '1' then
for i in 0 to LPM_PIPELINE loop
agbtmp(i) := '0';
agebtmp(i) := '0';
anebtmp(i) := '0';
aebtmp(i) := '0';
albtmp(i) := '0';
alebtmp(i) := '0';
end loop;
elsif CLOCK'event and CLOCK = '1' and CLKEN = '1' then
agbtmp(0 to LPM_PIPELINE-1) := agbtmp(1 to LPM_PIPELINE);
agebtmp(0 to LPM_PIPELINE-1) := agebtmp(1 to LPM_PIPELINE) ;
anebtmp(0 to LPM_PIPELINE-1) := anebtmp(1 to LPM_PIPELINE);
aebtmp(0 to LPM_PIPELINE-1) := aebtmp(1 to LPM_PIPELINE);
albtmp(0 to LPM_PIPELINE-1) := albtmp(1 to LPM_PIPELINE);
alebtmp(0 to LPM_PIPELINE-1) := alebtmp(1 to LPM_PIPELINE);
end if;
end if;
end if;
AGB <= agbtmp(0);
AGEB <= agebtmp(0);
ANEB <= anebtmp(0);
AEB <= aebtmp(0);
ALB <= albtmp(0);
ALEB <= alebtmp(0);
end process;
end LPM_SYN;
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