?? 220model.vhd
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-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
entity LPM_COMPARE is
generic (LPM_WIDTH : positive;
LPM_REPRESENTATION : string := "UNSIGNED";
LPM_PIPELINE : integer := 0;
LPM_TYPE: string := "LPM_COMPARE";
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
AGB : out std_logic;
AGEB : out std_logic;
AEB : out std_logic;
ANEB : out std_logic;
ALB : out std_logic;
ALEB : out std_logic);
end LPM_COMPARE;
architecture LPM_SYN of LPM_COMPARE is
component LPM_COMPARE_SIGNED
generic (LPM_WIDTH : positive;
LPM_PIPELINE : integer := 0;
LPM_TYPE: string := "LPM_COMPARE";
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
AGB : out std_logic;
AGEB : out std_logic;
AEB : out std_logic;
ANEB : out std_logic;
ALB : out std_logic;
ALEB : out std_logic);
end component;
component LPM_COMPARE_UNSIGNED
generic (LPM_WIDTH : positive;
LPM_PIPELINE : integer := 0;
LPM_TYPE: string := "LPM_COMPARE";
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTH-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTH-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
AGB : out std_logic;
AGEB : out std_logic;
AEB : out std_logic;
ANEB : out std_logic;
ALB : out std_logic;
ALEB : out std_logic);
end component;
begin
L1: if LPM_REPRESENTATION = "UNSIGNED" generate
U1: LPM_COMPARE_UNSIGNED
generic map (LPM_WIDTH => LPM_WIDTH, LPM_PIPELINE => LPM_PIPELINE,
LPM_TYPE => LPM_TYPE, LPM_HINT => LPM_HINT)
port map (DATAA => DATAA, DATAB => DATAB, ACLR => ACLR,
CLOCK => CLOCK, AGB => AGB, AGEB => AGEB, CLKEN => CLKEN,
AEB => AEB, ANEB => ANEB, ALB => ALB, ALEB => ALEB);
end generate;
L2: if LPM_REPRESENTATION = "SIGNED" generate
U2: LPM_COMPARE_SIGNED
generic map (LPM_WIDTH => LPM_WIDTH, LPM_PIPELINE => LPM_PIPELINE,
LPM_TYPE => LPM_TYPE, LPM_HINT => LPM_HINT)
port map (DATAA => DATAA, DATAB => DATAB, ACLR => ACLR,
CLOCK => CLOCK, AGB => AGB, AGEB => AGEB, CLKEN => CLKEN,
AEB => AEB, ANEB => ANEB, ALB => ALB, ALEB => ALEB);
end generate;
end LPM_SYN;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use work.LPM_COMPONENTS.all;
entity LPM_MULT_SIGNED is
generic (LPM_WIDTHA : positive;
LPM_WIDTHB : positive;
--LPM_WIDTHS : positive;
LPM_WIDTHS : natural := 0;
LPM_WIDTHP : positive;
LPM_PIPELINE : integer := 0;
LPM_TYPE: string := "LPM_MULT";
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
end LPM_MULT_SIGNED;
architecture LPM_SYN of LPM_MULT_SIGNED is
signal FP : std_logic_vector(LPM_WIDTHS-1 downto 0);
type t_resulttmp IS ARRAY (0 to LPM_PIPELINE) of std_logic_vector(LPM_WIDTHP-1 downto 0);
begin
process (CLOCK, ACLR, DATAA, DATAB, SUM)
variable resulttmp : t_resulttmp;
begin
if LPM_PIPELINE >= 0 then
if LPM_WIDTHP >= LPM_WIDTHS then
resulttmp(LPM_PIPELINE) := (DATAA * DATAB) + SUM;
else
FP <= (DATAA * DATAB) + SUM;
resulttmp(LPM_PIPELINE) := FP(LPM_WIDTHS-1 downto LPM_WIDTHS-LPM_WIDTHP);
end if;
if LPM_PIPELINE > 0 then
if ACLR = '1' then
for i in 0 to LPM_PIPELINE loop
resulttmp(i) := (OTHERS => '0');
end loop;
elsif CLOCK'event and CLOCK = '1' and CLKEN = '1' then
resulttmp(0 to LPM_PIPELINE - 1) := resulttmp(1 to LPM_PIPELINE);
end if;
end if;
end if;
RESULT <= resulttmp(0);
end process;
end LPM_SYN;
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
entity LPM_MULT_UNSIGNED is
generic (LPM_WIDTHA : positive;
LPM_WIDTHB : positive;
--LPM_WIDTHS : positive;
LPM_WIDTHS : natural := 0;
LPM_WIDTHP : positive;
LPM_PIPELINE : integer := 0;
LPM_TYPE: string := "LPM_MULT";
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS => '0');
RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
end LPM_MULT_UNSIGNED;
architecture LPM_SYN of LPM_MULT_UNSIGNED is
signal FP : std_logic_vector(LPM_WIDTHS-1 downto 0);
type t_resulttmp IS ARRAY (0 to LPM_PIPELINE) of std_logic_vector(LPM_WIDTHP-1 downto 0);
begin
process (CLOCK, ACLR, DATAA, DATAB, SUM)
variable resulttmp : t_resulttmp;
begin
if LPM_PIPELINE >= 0 then
if LPM_WIDTHP >= LPM_WIDTHS then
resulttmp(LPM_PIPELINE) := (DATAA * DATAB) + SUM;
else
FP <= (DATAA * DATAB) + SUM;
resulttmp(LPM_PIPELINE) := FP(LPM_WIDTHS-1 downto LPM_WIDTHS-LPM_WIDTHP);
end if;
if LPM_PIPELINE > 0 then
if ACLR = '1' then
for i in 0 to LPM_PIPELINE loop
resulttmp(i) := (OTHERS => '0');
end loop;
elsif CLOCK'event and CLOCK = '1' and CLKEN = '1' then
resulttmp(0 to LPM_PIPELINE - 1) := resulttmp(1 to LPM_PIPELINE);
end if;
end if;
end if;
RESULT <= resulttmp(0);
end process;
end LPM_SYN;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use work.LPM_COMPONENTS.all;
entity LPM_MULT is
generic (LPM_WIDTHA : positive;
LPM_WIDTHB : positive;
--LPM_WIDTHS : positive;
LPM_WIDTHS : natural := 0;
LPM_WIDTHP : positive;
LPM_REPRESENTATION : string := "UNSIGNED";
LPM_PIPELINE : integer := 0;
LPM_TYPE: string := "LPM_MULT";
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS => '0');
RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
end LPM_MULT;
architecture LPM_SYN of LPM_MULT is
component LPM_MULT_UNSIGNED
generic (LPM_WIDTHA : positive;
LPM_WIDTHB : positive;
--LPM_WIDTHS : positive;
LPM_WIDTHS : natural := 0;
LPM_WIDTHP : positive;
LPM_PIPELINE : integer := 0;
LPM_TYPE: string := "LPM_MULT";
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS => '0');
RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
end component;
component LPM_MULT_SIGNED
generic (LPM_WIDTHA : positive;
LPM_WIDTHB : positive;
--LPM_WIDTHS : positive;
LPM_WIDTHS : natural := 0;
LPM_WIDTHP : positive;
LPM_PIPELINE : integer := 0;
LPM_TYPE: string := "LPM_MULT";
LPM_HINT : string := "UNUSED");
port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);
DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS => '0');
RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));
end component;
begin
L1: if LPM_REPRESENTATION = "UNSIGNED" generate
U1: LPM_MULT_UNSIGNED
generic map (LPM_WIDTHA => LPM_WIDTHA,
LPM_WIDTHB => LPM_WIDTHB, LPM_WIDTHS => LPM_WIDTHS,
LPM_WIDTHP => LPM_WIDTHP, LPM_PIPELINE => LPM_PIPELINE,
LPM_TYPE => LPM_TYPE, LPM_HINT => LPM_HINT)
port map (DATAA => DATAA, DATAB => DATAB, ACLR => ACLR, CLKEN => CLKEN,
SUM => SUM, CLOCK => CLOCK, RESULT => RESULT);
end generate;
L2: if LPM_REPRESENTATION = "SIGNED" generate
U1: LPM_MULT_SIGNED
generic map (LPM_WIDTHA => LPM_WIDTHA,
LPM_WIDTHB => LPM_WIDTHB, LPM_WIDTHS => LPM_WIDTHS,
LPM_WIDTHP => LPM_WIDTHP, LPM_PIPELINE => LPM_PIPELINE,
LPM_TYPE => LPM_TYPE, LPM_HINT => LPM_HINT)
port map (DATAA => DATAA, DATAB => DATAB, ACLR => ACLR, CLKEN => CLKEN,
SUM => SUM, CLOCK => CLOCK, RESULT => RESULT);
end generate;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.LPM_COMPONENTS.all;
entity LPM_DIVIDE is
generic (LPM_WIDTHN : positive;
LPM_WIDTHD : positive;
--LPM_WIDTHQ : positive;
--LPM_WIDTHR : positive;
LPM_NREPRESENTATION : string := "UNSIGNED";
LPM_DREPRESENTATION : string := "UNSIGNED";
LPM_PIPELINE : integer := 0;
LPM_TYPE : string := "LPM_DIVIDE";
LPM_HINT : string := "UNUSED");
port (NUMER : in std_logic_vector(LPM_WIDTHN-1 downto 0);
DENOM : in std_logic_vector(LPM_WIDTHD-1 downto 0);
ACLR : in std_logic := '0';
CLOCK : in std_logic := '0';
CLKEN : in std_logic := '1';
QUOTIENT : out std_logic_vector(LPM_WIDTHN-1 downto 0);
REMAIN : out std_logic_vector(LPM_WIDTHD-1 downto 0));
end LPM_DIVIDE;
architecture behave of lpm_divide is
type qpipeline is array (0 to lpm_pipeline) of std_logic_vector(LPM_WIDTHN-1 downto 0);
type rpipeline is array (0 to lpm_pipeline) of std_logic_vector(LPM_WIDTHD-1 downto 0);
begin
process (aclr, clock, numer, denom)
variable tmp_quotient : qpipeline;
variable tmp_remain : rpipeline;
variable int_numer, int_denom, int_quotient, int_remain : integer := 0;
variable signed_quotient : signed(LPM_WIDTHN-1 downto 0);
variable unsigned_quotient : unsigned(LPM_WIDTHN-1 downto 0);
begin
if (lpm_nrepresentation = "UNSIGNED" ) then
int_numer := conv_integer(unsigned(numer));
else -- signed
int_numer := conv_integer(signed(numer));
end if;
if (lpm_drepresentation = "UNSIGNED" ) then
int_denom := conv_integer(unsigned(denom));
else -- signed
int_denom := conv_integer(signed(denom));
end if;
if int_denom = 0 then
int_quotient := 0;
int_remain := 0;
else
int_quotient := int_numer mod int_denom;
int_remain := int_numer rem int_denom;
end if;
signed_quotient := conv_signed(int_quotient, LPM_WIDTHN);
unsigned_quotient := conv_unsigned(int_quotient, LPM_WIDTHN);
tmp_remain(lpm_pipeline) := conv_std_logic_vector(int_Remain, LPM_WIDTHD);
if ((lpm_nrepresentation = "UNSIGNED") and (lpm_drepresentation = "UNSIGNED")) then
tmp_quotient(lpm_pipeline) := conv_std_logic_vector(unsigned_quotient, LPM_WIDTHN);
else
tmp_quotient(lpm_pipeline) := conv_std_logic_vector(signed_quotient, LPM_WIDTHN);
end if;
if lpm_pipeline > 0 then
if aclr = '1' then
for i in 0 to lpm_pipeline loop
tmp_quotient(i) := (OTHERS => '0');
tmp_remain(i) := (OTHERS => '0');
end loop;
elsif clock'event and clock = '1' then
if clken = '1' then
tmp_quotient(0 to lpm_pipeline-1) := tmp_quotient(1 to lpm_pipeline);
tmp_remain(0 to lpm_pipeline-1) := tmp_remain(1 to lpm_pipeline);
end if;
end if;
end if;
quotient <= tmp_quotient(0);
remain <= tmp_remain(0);
end process;
end behave;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;
use work.LPM_COMPONENTS.all;
entity LPM_ABS is
generic (LPM_WIDTH : positive;
LPM_TYPE: string := "LPM_ABS";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);
OVERFLOW : out std_logic);
end LPM_ABS;
architecture LPM_SYN of LPM_ABS is
begin
process(DATA)
begin
if (DATA = -2 ** (LPM_WIDTH-1)) then
OVERFLOW <= '1';
RESULT <= (OTHERS => 'X');
elsif DATA < 0 then
RESULT <= 0 - DATA;
OVERFLOW <= '0';
else
RESULT <= DATA;
OVERFLOW <= '0';
end if;
end process;
end LPM_SYN;
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.LPM_COMPONENTS.all;
entity LPM_COUNTER is
generic (LPM_WIDTH : positive;
LPM_MODULUS: natural := 0;
LPM_DIRECTION : string := "UNUSED";
LPM_AVALUE : string := "UNUSED";
LPM_SVALUE : string := "UNUSED";
LPM_PVALUE : string := "UNUSED";
LPM_TYPE: string := "LPM_COUNTER";
LPM_HINT : string := "UNUSED");
port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0):= (OTHERS => '0');
CLOCK : in std_logic ;
CLK_EN : in std_logic := '1';
CNT_EN : in std_logic := '1';
UPDOWN : in std_logic := '1';
SLOAD : in std_logic := '0';
SSET : in std_logic := '0';
SCLR : in std_logic := '0';
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